A 0.4V 320Mb/s 28.7µW 1024-bit configurable multiplier for subthreshold SOC encryption

Shi, Weiwei; Choy, Chiu-Sing

doi:10.1109/socc.2016.7905451

Cited by 1 publication

(5 citation statements)

References 8 publications

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“…If the propagation delay is rippled for three horizontally cascaded compressors, then three compressors must be considered in the simulation environment. This fact has been presumed for the architectures reported in [9], [10], [12], [13], [14], [18] and [19] (similar as Figure 2). Meanwhile, in the simulation environment, the propagation delay has been measured from the point that the earliest input transition reaches 50% of V dd , to the point where the latest output signal rises to 50% of the V dd voltage.…”

Section: Simulation Resultssupporting

confidence: 75%

“…In [15] and [19], gate-level simplification has been utilized for the design of 6-2 compressor. However, the critical path delay which belongs to output is still 5 XOR gates.…”

Section: The 6-compressormentioning

confidence: 99%

“…Post-layout simulations using HSPICE for TSMC standard 90nm CMOS technology along with 0.9V power supply have been carried out to measure the delay, and power consumption of the proposed 6-2 compressor and the works reported in [10], [18] and [19] which are redesigned and optimized here to make a fair comparison. Figure 10 illustrates the results for the correct functionality of the proposed architecture along with delay measurements.…”

Section: The 6-2 Compressormentioning

confidence: 99%

“…The results indicate that the lowest PDP value belongs to the proposed architecture. The design reported in [19], which has a delay value of about 481ps will need 53% more time to produce the output compared to the designed scheme. Also, the measurement results for the power dissipation at the operating frequency of 100MHz demonstrate that the proposed compressor circuit has the lowest value of power consumption, while the design reported in [10] which shows the lowest power consumption among the competitors, consumes 6% more power compared to the proposed circuit.…”

Section: The 6-2 Compressormentioning

confidence: 99%

“…The structure of a 6-2 compressor consists of three horizontal paths which transfer their corresponding bits to the adjacent block. Although several works have been introduced over recent years for hardware implementation of this structure [10,15,16,17,18,19], none of them could achieve latencies less than 5 XOR logic gates.…”

Section: Introductionmentioning

confidence: 99%

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CMOS High-Performance 5-2 and 6-2 Compressors for High-Speed Parallel Multipliers

Rahnamaei

2020

Informacije MIDEM

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In this article, the design procedure for high-speed 5-2 and 6-2 compressors, along with their analysis, has been discussed. With the help of the combinational logic consisting of the 4-2 compressor and 3-2 counter blocks, a high-performance structure for 6-2 compressor has been achieved, which shows significant speed improvement over previous architectures. The optimization has been carried out by reducing the carry rippling issue between the adjacent compressor structures. Also, the help of some modifications, the proposed 6-2 compressor will turn into a 5-2 compressor where the latency of the critical path has considerably been reduced, illustrating the superiority of designed circuits. The corresponding latencies of the proposed 5-2 and 6-2 structures are equal to 3.5 and 4 XOR logic gates, respectively, demonstrating speed boosting of 15% and 20% compared to the best-reported architectures. In addition, the power consumption and the transistor count of proposed circuits are have remained at a moderate level. Therefore, by considering the Power-Delay Product (PDP), our work will be a good choice for high-speed parallel multiplier design. Post-layout simulation results based on TSMC 90nm standard CMOS process and 0.9V power supply have been presented to confirm the correct functionality of the implemented compressors. These results have also been used as a fair comparison infrastructure between the proposed works and redesignated architectures of the previously reported schemes.

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Section: Simulation Resultssupporting

confidence: 75%

“…In [15] and [19], gate-level simplification has been utilized for the design of 6-2 compressor. However, the critical path delay which belongs to output is still 5 XOR gates.…”

Section: The 6-compressormentioning

confidence: 99%