A 0.2V, 7.5 &amp;#x03BC;W, 20 kHz &amp;#x03A3;&amp;#x0394; modulator with 69 dB SNR in 90 nm CMOS

Wismar, U.; Wisland, Dag T.; Andreani, Pietro

doi:10.1109/esscirc.2007.4430281

Cited by 28 publications

(31 citation statements)

References 11 publications

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“…If the number of zero-crossings of the FM signal during T s is less than two, it is possible to realize the structure in figure 3(a) with only two D-flipflops (DFFs), and an XOR-gate used for subtraction, as illustrated in figure 3(b). Due to its simple implementation, the first order single-bit FDSM is a viable choice for WSNN applications because of its potential for low power consumption and low voltage operating requirements (Wismar et al, 2007). In this case, the resolution of the converter is given by (Høvin et al, 1997) SQNR dB = 20 log 10 √ 2 f d f s − 10 log 10 π 2 36…”

Section: Fig 2 Fdsm Overviewmentioning

confidence: 99%

“…Several low-power ADC topologies adapted for sensor interfacing have been reported in the last few years (Yang & Sarpeshkar, 2005;Kim & Cho, 2006;Wismar et al, 2007;Taillefer & Roberts, 2007). Among them, some are utilizing the time-domain instead of the amplitudedomain to reduce the sensitivity to technology and power supply scaling (Kim & Cho, 2006;Wismar et al, 2007;Taillefer & Roberts, 2007). The non-feedback modulator for A/D conversion was introduced in Høvin et al (1995); Høvin et al (1997).…”

Section: Introductionmentioning

confidence: 99%

“…This requirement eliminates both conventional CT and SC ∆Σ modulators as these approaches require large amounts of power at low supply voltages to attain reasonable performance. Several low-power ADC topologies adapted for sensor interfacing have been reported in the last few years (Yang & Sarpeshkar, 2005;Kim & Cho, 2006;Wismar et al, 2007;Taillefer & Roberts, 2007). Among them, some are utilizing the time-domain instead of the amplitudedomain to reduce the sensitivity to technology and power supply scaling (Kim & Cho, 2006;Wismar et al, 2007;Taillefer & Roberts, 2007).…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Low-power Sensor Interfacing and MEMS for Wireless Sensor Networks

Michaelsen¹,

Ramstad²,

Wisland³

et al. 2011

Wireless Sensor Networks

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Section: Fig 2 Fdsm Overviewmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Low-power Sensor Interfacing and MEMS for Wireless Sensor Networks

Michaelsen¹,

Ramstad²,

Wisland³

et al. 2011

Wireless Sensor Networks

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“…It is shown that VCO-based converters can achieve a high energy efficiency [33,46]. Even though closed-loop converters achieve good resolution [36,37,47], they use analog components limiting the possibility of a full digital implementation.…”

Section: Chapter 4 Discussion and Future Workmentioning

confidence: 99%

“…Digital intensive designs are demonstrated in [29,[31][32][33][34]. The impact of circuit non-idealities on VCO-based open-loop converters is analyzed in [30].…”

Section: Examples From the Literaturementioning

confidence: 99%

Design of VCO-based ADCs

Unnikrishnan¹

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Today's complex electronic systems with billions of transistors on a single die are enabled by the aggressive scaling down of the device feature size at an exponential rate as predicted by the Moore's law. Digital circuits benefit from technology scaling to become faster, more energy efficient as well as more area efficient as the feature size is scaled down. Moreover, digital design also benefits from mature CAD tools that simplify the design and cross-technology porting of complex systems, leveraging on a cell-based design methodology. On the other hand, the design of analog circuits is getting increasingly difficult as the feature size scales down into the deep nanometer regime due to a variety of reasons like shrinking voltage headroom, reducing intrinsic gain of the devices, increasing noise coupling between circuit nodes due to shorter distances etc. Furthermore, analog circuits are still largely designed with a full custom design flow that makes their design and porting tedious, slow, and expensive. In this context, it is attractive to consider realizing analog/mixed-signal circuits using standard digital components. This leads to scaling-friendly mixed-signal blocks that can be designed and ported using the existing CAD framework available for digital design. The concept is already being applied to mixed-signal components like frequency synthesizers where all-digital architectures are synthesized using standard cells as basic components. This can be extended to other mixed-signal blocks like digital-to-analog and analogto-digital converters as well, where the latter is of particular interest in this thesis.A voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC) is an attractive architecture to achieve all-digital analog-todigital conversion due to favorable properties like shaping of the quantization error, inherent anti-alias filtering etc. Here a VCO operates as a signal integrator as well as a quantizer. A converter employing a ring oscillator as the VCO lends itself to an all-digital implementation.iii In this dissertation, we explore the design of VCO-based ADCs synthesized using digital standard cells with the long-term goal of achieving high performance data converters built from low accuracy switch components. In a first step, an ADC is designed using vendor supplied standard cells and fabricated in a 65 nm CMOS process. The converter delivers an 8-bit ENOB over a 25 MHz bandwidth while consuming 3.3 mW of power resulting in an energy efficiency of 235 fJ/step (Walden FoM). Then we utilize standard digital CAD tools to synthesize converter designs that are fully described using a hardware description language. A polynomial-based digital post-processing scheme is proposed to correct for the VCO nonlinearity. In addition, pulse modulation schemes like delta modulation and asynchronous sigma-delta modulation are used as a signal pre-coding scheme, in an attempt to reduce the impact of VCO nonlinearity on converter performance. In order to investigate the scaling benefit...

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VCO-Based Wideband Continuous-Time Sigma-Delta Analog-to-Digital Converters

Perrott

2011

Analog Circuit Design

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A 0.2V, 7.5 μW, 20 kHz ΣΔ modulator with 69 dB SNR in 90 nm CMOS

Cited by 28 publications

References 11 publications

Low-power Sensor Interfacing and MEMS for Wireless Sensor Networks

Low-power Sensor Interfacing and MEMS for Wireless Sensor Networks

Design of VCO-based ADCs

VCO-Based Wideband Continuous-Time Sigma-Delta Analog-to-Digital Converters

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