A 0.28pJ/b 2Gb/s/ch Transceiver in 90nm CMOS for 10mm On-Chip interconnects

Abstract

ISSCC 2007 / SESSION 22 / DIGITAL CIRCUIT INNOVATIONS / 22.9 22.9 A 0.28pJ/b 2Gb/s/ch Transceiver in 9Onm CMOS The schematic of the receiver implementation is shown in Fig. for 10mm On-Chip interconnects Fig. 22.9.2). TheThe bandwidth of global on-chip interconnects in modern CMOS total area of the receiver is 117 gm2 (324m2 for the DFE part) processes is limited by their high resistance and capacitance [1]. Repeaters that are used to speed up these interconnects consume The chip micrograph is shown in Fig. 22.9

Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects

“…In [20] Ho et al presented more details on their work and provided a qualitative intuitive explanation of the capacitive driver technique. This paper extends our work in [14]. With the use of an s-parameter model, we will analyze the transfer function of RC-limited interconnect showing that an ideal source or load impedance exists for which the transfer function becomes flat, as is desired for inter symbol interference and bandwidth.…”

“…3(c) [13], [14]. Now, the achievable data rate has increased about three times, slightly more than for current-sensing, again at the cost of a reduced maximum voltage swing.…”

“…In [14] we proposed to use decision feedback equalization (DFE), and will show here that this can be implemented at very low power penalty. DFE is well known in other communication areas, for example in inter-chip communication [18].…”

“…During ISSCC 2007, both Ho et al [13] and our research group [14] independently proposed to use a data transmitter with capacitive coupling to the interconnect, resulting in increased bandwidth and low power consumption due to a reduced voltage swing. In [20] Ho et al presented more details on their work and provided a qualitative intuitive explanation of the capacitive driver technique.…”

A Survey Addressing On-Chip Interconnect: Energy and Reliability Considerations

“…Capacitively driven links, proposed in [14] use a feed-forward AC-coupling capacitor in order to increase the effective signaling bandwidth of the channel while reducing the supply voltage. Reference [15][16][17][18] extend this approach by applying feed-forward equalization (FFE) and decision feedback equalization (DFE) techniques, used traditionally in high-speed serial transceivers for offchip links, to improve performance and reliability for long, on-chip interconnect wires. These proposed methods however result in either floating AC-coupled wires, which are are more susceptible to interference than actively driven nodes, or require static bias currents which burn power even when no signaling is taking place.…”