A 0.25μm CMOS 3b 12.5Gs/s frequency channelized receiver for serial-links

Abstract

As the speed of CMOS serial-links continues to improve, the achievable data bandwidth is limited by the off-chip environment such as wire losses in backplane traces and package parasitics. In such environments, well-known digital communication techniques such as coding, equalization, and multi-level signaling need to be employed to continue the increase of the serial-link data rates. Although increased digital processing capabilities allow the use of these techniques, the lack of available multi-bit ADCs has primarily limited their use. To achieve multi-bit data conversion at the signal Nyquist rate, a receiver architecture that decomposes the received wideband signal into multiple frequency subbands before digitizing at a much reduced frequency is designed and fabricated in 0.25µm CMOS process. This frequency-channelized receiver samples at an effective sampling frequency of 12.5GS/s with 3b resolution and requires no initial ADC offset compensation. The chip occupies 4.0mm 2 while consuming 1W at 2.5V supply. The functionality of the proposed receiver is demonstrated by correctly operating at 10Gsymbols/s in a channel with significant ISI.Existing multi-bit receiver architectures operate by time-interleaving parallel ADCs with each operating at a fraction of the symbol frequency [1]. A fundamental problem of such parallel architecture is the mismatches among the demultiplexing channels, which are especially pronounced when operating at high data rates, as small transistors with corresponding small input capacitance are employed to meet the bandwidth requirements. Another drawback is the high sensitivity to sampling jitter caused by the large amounts of aliasing of the wideband input signal.Instead of channelizing by time-interleaving ADCs, the received signal can be channelized into multiple frequency subbands with an ADC in each subband channel operating at a fraction of the effective sampling frequency [2]. An important advantage of channelizing in the frequency domain, instead of in the time domain, is that the digitized signal becomes less sensitive to channel mismatches and sampling jitter. Intuitively, this robustness results because the narrower signal bandwidth in each subband channel reduces the amount of aliasing caused by channel mismatches and sampling jitter. Another important advantage is that it obviates the need to generate accurately spaced clocks, which may become problematic as technology scales.The proposed frequency-channelized receiver is shown in Fig. 18.5.1(a). The received signal is channelized into three subbands by employing two quadrature mixers and low-pass filters. Figure 18.5.1(b) shows the relationship between the signal bandwidth and the local oscillator frequencies. To further relax the ADC sampling requirements, the channelized subbands are sampled by time-interleaving two 3b ADCs, each operating at 1.25GS/s. A total of 10 ADCs are employed to achieve an effective sampling frequency of 12.5GS/s.In the second and third subband channels, quadrature mixing is achieved by using ...

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“…2, includes four cross-coupled PMOS transistors, M 0 1 -M 0 4 [10,15]. The cross-coupled double-balanced structure ensures that the even-order non-linear components in the transistor voltageto-current characteristics cancel out through symmetry and the output voltage is the multiplication of the two input signals, V RF and V LO [10,15], given as:…”

“…Note that the required mixer frequencies are multiples of the first mixer frequency and can be implemented using a variety of techniques, for example using a PLL-based frequency multiplier block [10].…”

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“…where T is the sampling period of each subband ADC as specified in ( 3.3). have previously been used in [48] for an ADC system and in [49] for a serial link receiver; however, these systems had different digital reconstruction structures and aimed for lower resolutions and different applications.…”

“…The passive mixer, as shown in Figure 5.1, includes four cross-coupled PMOS transistors, M' 1 -M' 4 , operating in the triode region [49], [59]. The cross-coupled doublebalanced structure ensures that the even-order non-linear components in the transistor voltage-to-current characteristics almost cancel out through symmetry and the output voltage is the multiplication of the two input signals, V RF and V LO [49], [59], given as:…”

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