A 0.25–1.25-GHz High-Efficiency Power Amplifier With Computer-Aided Design Based on Optimized Impedance Solution Continuum

Jia, Pei; You, Fei; He, Songbai; Xi, Qi

doi:10.1109/lmwc.2018.2814483

Cited by 11 publications

(9 citation statements)

References 8 publications

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“…In a previous study, 9 two Verilog-A cells were established to represent lumped components, and the ultra-wide band (UWB) matching network was designed automatically using the impedance characteristics of the components. In studies, [10][11] the angles of the vector relationship between the reflection coefficient of the MN and the impedance region were formulated through appropriate mathematical tools and constraints, and the corresponding constrains in CAD were integrated automatic optimization design of MN. In another study, 12 a dualfrequency selective impedance matching technique was used to optimize impedances that extended lower and upper-frequency corners while checking the mismatch level for the center frequency.…”

Section: Introductionmentioning

confidence: 99%

A 18‐23 GHz power amplifier design using approximate optimal impedance region approach for satellite downlink

Zhao

et al. 2021

Int J RF Microw Comput Aided Eng

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This paper presents the design procedure of a K-band 0.1 μm GaAs pseudomorphic high electron mobility transistors (pHEMT) monolithic microwave integrated circuit (MMIC) for satellite communication downlinks. The method focuses on the selection and design of the matching network (MN) by applying the Approximate Optimal Impedance Region (AOIR) approach which is a composition of simple mathematical constraints. The AOIR approach overcomes the drawbacks of traditional MN design method which cannot control the reflection coefficient trajectory of the MN precisely. The method formulates the constraints through symbolic-graphic combinations with integrated functions of computer-aided design (CAD) tools. The impedance transformation trajectory of MN is combined to reduce the mismatch and the insertion loss using equations with multiple mathematical constraints to realize the automatic selection of the MN's topology. The AOIR method fully considers the underutilized characteristics of power amplifier (PA) and to maximize its performance in a balanced manner. The MMIC, was designed using the proposed technique, operates in 18 GHz-23 GHz with a gain of 27 dB and has an average P −1 dB of 27 dBm and PAE of 38% under the continuous wave (CW) drive signal.

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Section: Introductionmentioning

confidence: 99%

A 18‐23 GHz power amplifier design using approximate optimal impedance region approach for satellite downlink

Zhao

et al. 2021

Int J RF Microw Comput Aided Eng

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“…Reference [7] presents a high efficiency PA using realfrequency matching technology. A design approach based on optimized impedance solution continuum for broadband PA is proposed in [8]. In [9], a design method for dual-frequency Doherty power amplifier (DPA) using dual-frequency phase shift lines to improve performance is proposed.…”

Section: Introductionmentioning

confidence: 99%

Filtering Power Amplifier With Up to 4^th Harmonic Suppression

Xiao

2020

IEEE Access

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Unlike conventional conception that power amplifier and filter are regarded as two separate components and designed separately, this paper presents a high efficiency power amplifier with filtering capability, which is called filtering power amplifier. The proposed power amplifier integrates a bandpass filter as output matching network so that entire size is reduced to some extent. The filter will play the role of filtering and impedance matching simultaneously, and thus high-order harmonics are suppressed for output of the filtering power amplifier. For demonstration, an example of filtering power amplifier was designed, fabricated and measured. The measurement shows that it is featured by highly-selective bandpass response and good out-of-band performance. As high as 46.2 dB suppression can be achieved and extended over the forth-order harmonic. The example also retains the advantages of high efficiency and output power. The maximum output power can reach 40.5 dBm, and the maximum power-added efficiency is as high as 62%.

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“…The resistive feedback is easy to design, with the disadvantage of high power loss . Harmonic‐tuned amplifiers operating in high‐efficiency switch‐mode rely deeply on accurate harmonic impedance match, resulting in a limited bandwidth …”

Section: Introductionmentioning

confidence: 99%

“…2 Harmonic-tuned amplifiers operating in high-efficiency switch-mode rely deeply on accurate harmonic impedance match, 3 resulting in a limited bandwidth. 4,5 Stacked structure was firstly introduced to improve output power of PA. 6 With the continuous scaling in semiconductor technologies for a single kind of material, the breakdown voltage of a single device decreases; therefore, the level of the achievable output power is limited. Stacked configuration is one good solution to overcome this limitation.…”

Section: Introductionmentioning

confidence: 99%

Analysis and design of a stacked power amplifier with 196% fractional bandwidth using equivalent circuit model

Wang

et al. 2020

Int J RF Microw Comput Aided Eng

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Stacked structure is a good solution to overcome the low output voltage swing provided by a single device. When several devices are stacked, the bandwidth and output power are multiple times higher. This article analyzes the small‐signal voltage gain of the stacked structure, deriving the gain expression of the high‐frequency model and simplified model. Based on the specific device parameter, the different small‐signal voltage gains between the two models are compared and the designed stacked structure is proved to obtain a flat gain at low frequencies below about 3 GHz. To our best knowledge, this is the first article to analyze the gain flatness of stacked structure with two equivalent circuit models. To verify the stacked theory, a pseudomorphic high‐electron‐mobility transistor（PHEMT） power amplifier (PA) is implemented using 0.25 μm Gallium arsenide (GaAs) technology. The PA achieves an ultra‐high bandwidth of 30 MHz to 3 GHz and a linear gain of 21 dB ± 1.5 dB. At a 16‐V drain bias voltage, a saturated output power of higher than 2 W and a peak power‐added efficiency (PAE) of 44.1% are attained.

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A 0.25–1.25-GHz High-Efficiency Power Amplifier With Computer-Aided Design Based on Optimized Impedance Solution Continuum

Cited by 11 publications

References 8 publications

A 18‐23 GHz power amplifier design using approximate optimal impedance region approach for satellite downlink

A 18‐23 GHz power amplifier design using approximate optimal impedance region approach for satellite downlink

Filtering Power Amplifier With Up to 4^th Harmonic Suppression

Analysis and design of a stacked power amplifier with 196% fractional bandwidth using equivalent circuit model

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A 0.25–1.25-GHz High-Efficiency Power Amplifier With Computer-Aided Design Based on Optimized Impedance Solution Continuum

Cited by 11 publications

References 8 publications

A 18‐23 GHz power amplifier design using approximate optimal impedance region approach for satellite downlink

A 18‐23 GHz power amplifier design using approximate optimal impedance region approach for satellite downlink

Filtering Power Amplifier With Up to 4th Harmonic Suppression

Analysis and design of a stacked power amplifier with 196% fractional bandwidth using equivalent circuit model

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Product

Resources

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Filtering Power Amplifier With Up to 4^th Harmonic Suppression