A 0.18/spl mu/m CMOS implementation of an area efficient precise exception handling unit for processing-in-memory systems

Abstract

This paper describes the implementation of theexception handling mechanism in the second prototype version of the Data-Intensive Architecture (DIVA) processing-inmemory (PIM) chip. This implementation features architectural simplicity, low area (54289 p 2 ) , delay (2.643 nanosecond) and power consumption (7.6 milliwatts), and effective hardware support for complex cases of exception handling. This work provides a description of handling memory-access, execution and communication-related exceptions in an area-and powerefficient manner, which are key design specifications for DIVA.The current implementation has been tested by verifying various exceptions on DIVA-I1 PIM chips running at 140MHz in the memory system of a HP Itanium2-based Long's Peak server. The generic nature of the DIVA exceptions and their classification makes the current implementation suitable and easy for use in diverse microarchitectures with little modification.

Precise exception handling in discontinuous control flow scenarios for area-constrained systems

“…2). Multiple exceptions are handled based on a flexible priority assignment scheme [2]. Table I shows hardware-vectored exceptions and corresponding vector addresses.…”

“…Bits of the ESW are cleared to 0 by software setting corresponding bits in the ERR. The particular source of the exception is enabled by the mask register and globally enabled via an exception enable bit in PSW [2]. With the exception recognition, the mode is set to supervisor mode and the exception enable bit in PSW is automatically cleared.…”

“…To save the target instruction address, NADR is used to hold the address of the instruction that was issued after that pointed to by the FADR. NADR keeps the flow of the execution even in the case that the flow is not sequential, and it is mentioned in the previous work [2]. We build on this concept to add robustness to the mechanism by which FADR and NADR record correct return addresses upon exception recognition in a discontinuous flow without software help.…”

“…Even with this simplicity, the problem can still become difficult. A prior paper discussed a previous scheme for DIVA that placed too much burden on software to determine the return address [2]. Sometimes it is not possible to recover the processor state with a single program counter (PC) because of the discontinuous control flow with a branch instruction.…”