A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm

Zimmer, Brian; Venkatesan, Rangharajan; Shao, Yakun Sophia; Clemons, Jason; Fojtik, Matthew; Jiang, Nan; Keller, Ben; Klinefelter, Alicia; Pinckney, Nathaniel; Raina, Priyanka; Tell, Stephen G.; Zhang, Yanqing; Dally, William J.; Emer, Joel; Gray, C. Thomas; Keckler, Stephen W.; Khailany, Brucek

doi:10.23919/vlsic.2019.8778056

Cited by 41 publications

(21 citation statements)

References 1 publication

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“…A common peculiarity in all of these architectures is that the power consumption required to support FP operations is too demanding for their adoption in IoT end nodes or as ultra-low-power architectures. Recent trend is to equip IoT platforms e.g., microcontroller units like M4 and M7 [2] with FP unit, this is because with the scaling of technology below 40nm, the cost of an FP operation is getting near 1pJ/op [19], [25], so it has become affordable in terms of absolute power to use FP in IoT.…”

Section: Related Workmentioning

confidence: 99%

TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE

Prasad

Das

Martin

et al. 2020

2020 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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In recent years, Coarse Grain Reconfigurable Architecture (CGRA) accelerators have been increasingly deployed in Internet-of-Things (IoT) end nodes. A modern CGRA has to support and efficiently accelerate both integer and floating-point (FP) operations. In this paper, we propose an ultra-low-power tunableprecision CGRA architectural template, called TRANSprecision floating-point Programmable archItectuRE (TRANSPIRE), and its associated compilation flow supporting both integer and FP operations. TRANSPIRE employs transprecision computing and multiple Single Instruction Multiple Data (SIMD) to accelerate FP operations while boosting energy efficiency as well. Experimental results show that TRANSPIRE achieves a maximum of 10.06× performance gain and consumes 12.91× less energy w.r.t. a RISC-V based CPU with an enhanced ISA supporting SIMD-style vectorization and FP data-types, while executing applications for near-sensor computing and embedded machine learning, with an area overhead of 1.25× only.

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Section: Related Workmentioning

confidence: 99%

TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE

Prasad

Das

Martin

et al. 2020

2020 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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“…Core Placement Optimization for Many-Core Systems with RL 11:5 In Figure 3, we take Tianjic as an example to illustrate the typical multi-chip many-core architecture. Usually, multiple chips (e.g., 4 × 4 in Figure 3(a)) can be interconnected through offchip links such as low-voltage differential signaling (LVDS) [9], SerDes [7] and ground-referenced signaling (GRS) [89,96]. As illustrated in Figure 3(b), each chip includes an array of functional cores arranged by a 2D mesh network-on-chip (NoC), an on-chip router for off-chip communication and essential chip peripherals.…”

Section: Multi-chip Many-core Architecturesmentioning

confidence: 99%

“…We build an in-house simulator for the typical multi-chip many-core architecture illustrated in Figure 3. The overall system consists of a 4 × 4 chip array with 16 × 16 cores per chip, with the off-chip interconnect assumed as GRS [89,96]. Generally, the routing is based on the minimal path, with X-Y routing for both NoC and off-chip communication.…”

Section: Experiments Setupmentioning

confidence: 99%

“…Although all chips are functional in the multi-chip many-core system, different workloads may occupy different number of chips/cores, since in these spatially weight-stationary mappings, the number of cores consumed is kind of proportional to the model size. Configuration parameters are summarized in Table 1, which are collected from existing multi-chip many-core architectures [17,62,67,89,96]. As for hyperparameters in our RL-based approach, the learning rates of the actor and the critic are set as α θ = 0.0002 and α w = 0.001, with the discount factor γ = 0.98.…”

Section: Experiments Setupmentioning

confidence: 99%

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Core Placement Optimization for Multi-chip Many-core Neural Network Systems with Reinforcement Learning

Deng

et al. 2020

ACM Trans. Des. Autom. Electron. Syst.

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Multi-chip many-core neural network systems are capable of providing high parallelism benefited from decentralized execution, and they can be scaled to very large systems with reasonable fabrication costs. As multi-chip many-core systems scale up, communication latency related effects will take a more important portion in the system performance. While previous work mainly focuses on the core placement within a single chip, there are two principal issues still unresolved: the communication-related problems caused by the non-uniform, hierarchical on/off-chip communication capability in multi-chip systems, and the scalability of these heuristic-based approaches in a factorially growing search space. To this end, we propose a reinforcement-learning-based method to automatically optimize core placement through deep deterministic policy gradient, taking into account information of the environment by performing a series of trials (i.e., placements) and using convolutional neural networks to extract spatial features of different placements. Experimental results indicate that compared with a naive sequential placement, the proposed method achieves 1.99× increase in throughput and 50.5% reduction in latency; compared with the simulated annealing, an effective technique to approximate the global optima in an extremely large search space, our method improves the throughput by 1.22× and reduces the latency by 18.6%. We further demonstrate that our proposed method is capable to find optimal placements taking advantages of different communication properties caused by different system configurations, and work in a topology-agnostic manner. CCS Concepts: • Computer systems organization → Architectures; Parallel architectures; • Computing methodologies → Reinforcement learning;

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“…The error backpropagation method is known as an efficient method for calculating gradients in the field of deep neural network machine learning for updating parameters using the gradient descent method [24]. Further speed improvement can be easily realized through using the GPGPU technique, which is again well established and under significant development in the field of deep learning [25].…”

Section: Introductionmentioning

confidence: 99%

Quantum Circuit Learning with Error Backpropagation Algorithm and Experimental Implementation

Watabe

Shiba

Chen³

et al. 2021

Quantum Reports

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Quantum computing has the potential to outperform classical computers and is expected to play an active role in various fields. In quantum machine learning, a quantum computer has been found useful for enhanced feature representation and high-dimensional state or function approximation. Quantum–classical hybrid algorithms have been proposed in recent years for this purpose under the noisy intermediate-scale quantum computer (NISQ) environment. Under this scheme, the role played by the classical computer is the parameter tuning, parameter optimization, and parameter update for the quantum circuit. In this paper, we propose a gradient descent-based backpropagation algorithm that can efficiently calculate the gradient in parameter optimization and update the parameter for quantum circuit learning, which outperforms the current parameter search algorithms in terms of computing speed while presenting the same or even higher test accuracy. Meanwhile, the proposed theoretical scheme was successfully implemented on the 20-qubit quantum computer of IBM Q, ibmq_johannesburg. The experimental results reveal that the gate error, especially the CNOT gate error, strongly affects the derived gradient accuracy. The regression accuracy performed on the IBM Q becomes lower with the increase in the number of measurement shot times due to the accumulated gate noise error.

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A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm

Cited by 41 publications

References 1 publication

TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE

TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE

Core Placement Optimization for Multi-chip Many-core Neural Network Systems with Reinforcement Learning

Quantum Circuit Learning with Error Backpropagation Algorithm and Experimental Implementation

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