A 0.076 mm2 12 b 26.5 mW 600 MS/s 4-Way Interleaved Subranging SAR- $\Delta \Sigma $ ADC With On-Chip Buffer in 28 nm CMOS

Venca, Alessandro; Ghittori, N.; Bosi, Alessandro; Nani, Claudio

doi:10.1109/jssc.2016.2591553

Cited by 24 publications

(6 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Ref. [4] adopted 4-way interleaved and hybrid architecture achieve high speed, but capacitor mismatch and channel mismatch limited the precision due to absence of calibration. Ref.…”

Section: Introductionmentioning

confidence: 99%

Low Power SAR ADC Design with Digital Background Calibration Algorithm

Chen

Liang

et al. 2020

Symmetry

View full text Add to dashboard Cite

This paper proposed a digital background calibration algorithm with positive and negative symmetry error tolerance to remedy the capacitor mismatch for successive approximation register analog-to-digital converters (SAR ADCs). Compensate for the errors caused by capacitor mismatches and improve the ADC performance. Combination with a tri-level switching scheme based on the common-mode voltage Vcm to achieve capacitor reduction and high switching energy efficiency. The proposed calibration algorithm significantly improves capacitor mismatch without resorting to extensive computation or dedicated circuits. The active area is 0.046 mm2 in 40 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The post-simulation results show the effective number of bits (ENOB) improves from 8.23 bits to 11.36 bits, signal-to-noise-and distortion ratio (SNDR) improves from 51.33 dB to 70.15 dB, respectively, before and after calibration. This improves the spurious-free dynamic range (SFDR) by 24.13 dB, from 61.50 dB up to 85.63 dB. The whole ADC’s power consumption is only 0.3564 mW at sampling rate fs =2 MS/s and Nyquist input frequency, with a figure-of-merit (FOM) 67.8 fJ/conv.-step.

show abstract

“…Ref. [4] adopted 4-way interleaved and hybrid architecture achieve high speed, but capacitor mismatch and channel mismatch limited the precision due to absence of calibration. Ref.…”

Section: Introductionmentioning

confidence: 99%

Low Power SAR ADC Design with Digital Background Calibration Algorithm

Chen

Liang

et al. 2020

Symmetry

View full text Add to dashboard Cite

show abstract

“…See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. beyond 200× [4] and sometimes an off-chip capacitor is adopted [5]. In order to get rid of both a power-hungry buffer and a large C DEC , some solutions have been presented using a small C DEC driving the DAC passively and eliminating the signal dependence of the reference voltage drop as shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

A 10-b 20-MS/s SAR ADC With DAC-Compensated Discrete-Time Reference Driver

Liu

Roermund

Harpe

2019

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

DOI to the publisher's website.• The final author version and the galley proof are versions of the publication after peer review.• The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publication General rightsCopyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.• Users may download and print one copy of any publication from the public portal for the purpose of private study or research. • You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal.If the publication is distributed under the terms of Article 25fa of the Dutch Copyright Act, indicated by the "Taverne" license above, please follow below link for the End User Agreement:

show abstract

“…1, in which the quantization, digital-to-analog conversion and summation in the dashed box could be realized by reusing only one SAR ADC. By using this new modulator structure with an asynchronous SAR quantizer using an improved switching scheme [6,7,8,9,10,11,12,13], the number and value of capacitors can be reduced greatly. The requirements of the analog adder and dynamic element matching (DEM) circuits in the modulator can be relaxed, which introduces a significant reduction in the power consumption and area occupation.…”

Section: Introductionmentioning

confidence: 99%

A hybrid Sigma-Delta modulator with reusable SAR quantizer

Yin

Xin

et al. 2019

IEICE Electron. Express

View full text Add to dashboard Cite

A novel energy-efficient hybrid multi-bit Sigma-Delta modulator with a reusable successive approximation register (SAR) quantizer is proposed. By reusing the SAR quantizer, sampling capacitors in the first integrator of the modulator could be eliminated and almost rail to rail input signal range could be achieved by the modulator without the requirement of a high-swing analog adder in front of the quantizer, which is usually power hungry in multi-bit modulators. In this way, small capacitors could be used to meet the thermal noise requirements, thus reducing the power and area consumption. With an improved switching procedure, only a half number of the unit capacitors are needed in the SAR quantizer, which further reduce the area consumption.

show abstract

A 0.076 mm2 12 b 26.5 mW 600 MS/s 4-Way Interleaved Subranging SAR- $\Delta \Sigma $ ADC With On-Chip Buffer in 28 nm CMOS

Cited by 24 publications

References 12 publications

Low Power SAR ADC Design with Digital Background Calibration Algorithm

Low Power SAR ADC Design with Digital Background Calibration Algorithm

A 10-b 20-MS/s SAR ADC With DAC-Compensated Discrete-Time Reference Driver

A hybrid Sigma-Delta modulator with reusable SAR quantizer

Contact Info

Product

Resources

About