A 0.0053-mm<sup>2</sup> 6-bit Fully-Standard-Cell-Based Synthesizable SAR ADC in 65 nm CMOS

Ojima, Naoki; Xu, Zule; Iizuka, Tetsuya

doi:10.1109/newcas44328.2019.8961218

Cited by 10 publications

(6 citation statements)

References 5 publications

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“…Following the above-described context, research trends are towards designing analog blocks using digital standard cells, either to mimic the behavior of analog building blocks [29][30][31][32][33][34] or by implementing analog functions in the digital domain [7,9,10,[35][36][37][38][39][40][41][42][43][44][45][46][47][48][49]. A standard-cell-based implementation of analog functions simplifies the portability of designs among different technologies, and the speed vs. supply voltage reconfigurability.…”

Section: Introductionmentioning

confidence: 99%

Standard-Cell-Based Comparators for Ultra-Low Voltage Applications: Analysis and Comparisons

Della Sala,

Centurelli,

Scotti

et al. 2023

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This work is focused on the performance of three different standard-cell-based comparator topologies, considering ultra-low-voltage (ULV) operation. The main application scenarios in which standard-cell-based comparators can be exploited are considered, and a set of figures of merit (FoM) to allow an in-depth comparison among the different topologies is introduced. Then, a set of simulation testbenches are defined in order to simulate and compare the considered topologies implemented in both a 130 nm technology and a 28 nm FDSOI CMOS process. Propagation delay, power consumption and power–delay product are evaluated for different values of the input common mode voltage, as a function of input differential amplitude, and in different supply voltage and temperature conditions. Monte Carlo simulations to evaluate the input offset voltage under mismatch variations are also provided. Simulation results show that the performances of the different comparator topologies are strongly dependent on the input common mode voltage, and that the best values for all the performance figures of merit are achieved by the comparator based on three-input NAND gates, with the only limitation being its non-rail-to-rail input common mode range (ICMR). The performances of the considered comparator topologies have also been simulated for different values of the supply voltage, ranging from 0.3 V to 1.2 V, showing that, even if standard-cell-based comparators can be operated at higher supply voltages by scaling their performances accordingly, the best values of the FoMs are achieved for VDD = 0.3 V.

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Section: Introductionmentioning

confidence: 99%

Standard-Cell-Based Comparators for Ultra-Low Voltage Applications: Analysis and Comparisons

Della Sala,

Centurelli,

Scotti

et al. 2023

Chips

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“…In this design approach, all circuit building blocks are implemented through standard-cells taken from the digital library and coded in a hardware description language, which can then be synthesized from commercial standard-cell libraries and automatically placed and routed using electronic design automation (EDA) tools. Compared to conventional analog implementations, standard-cell-based analog implementations significantly shorten the design time and cost [20][21][22][23][24][25][26][27][28][29][30][31][32].…”

Section: Introductionmentioning

confidence: 99%

A High Performance 0.3 V Standard-Cell-Based OTA Suitable for Automatic Layout Flow

2023

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In this paper, we propose a novel standard-cell-based OTA architecture based on an improved version of the differential to single-ended converter, previously proposed by the authors, on a novel standard-cell-based basic voltage amplifier block. Due to a replica-bias approach, the basic voltage amplifier exhibits a well-defined output static voltage to allow easy cascadability. Another feature of the basic voltage amplifier is to provide a low output impedance to allow dominant pole compensation at the output of the cascade of several stages. An ultra-low voltage (ULV) standard-cell-based OTA based on the proposed architecture and building blocks has been designed referring to the standard-cell library of a 130-nm CMOS process with a supply voltage of 0.3 V. The layout of the OTA has been implemented by following an automatic layout flow within a commercial tool for the place-and-route of digital circuits. Simulation results have shown a differential gain of 50 dB with a gain–bandwidth product of 10 MHz when driving a 150 pF load capacitance. Good robustness is achieved under PVT variations, in particular for voltage gain, offset voltage, and phase margin. State-of-the-art small signal figures of merit and limited area footprint are key characteristics of the proposed amplifier.

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“…With the aim of speeding up the design time and to drastically reduce the area usage of analog building blocks, researchers have recently focused on optimizing and refining novel layout strategies, searching for a way to automate the design flow of analog blocks by using some features, such as the automatic place and route strategies for standard-cell based circuits, typically adopted in the digital design flow to implement fully-synthesizable comparators [12]- [15], ADCs [16]- [19], DACs [20], LDOs [21]- [23] and OTAs [2], [24]- [27].…”

Section: Introductionmentioning

confidence: 99%

A Novel Differential to Single-Ended Converter for Ultra-Low-Voltage Inverter-Based OTAs

2022

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For the design of inverter-based OTAs with differential input and single-ended output, the differential to single-ended (D2S) converter is a key building block. In fact, the performance of the D2S strongly affects the overall common-mode rejection ratio (CMRR) and input common-mode range (ICMR) of the whole OTA. In recent literature, inverter-based OTAs rely on a D2S topology based on an inverter driving another inverter with the input and output tight together which behaves as a "diode" connected device to implement a voltage gain approximately equal to −1. However, since this approach is based on the matching of the inverters, the performance of this D2S results sensitive to PVT variations if the bias point of the inverters is not properly stabilized. In this paper we present a novel topology of inverterbased D2S converter, exploiting an auxiliary, standard-cell-based, error amplifier and a local feedback loop. The proposed D2S, compared to the conventional one, exhibits higher CMRR, improved ICMR and better robustness with respect to PVT variations. We present also an ULV, standard-cell-based OTA, which exploits the proposed D2S converter and shows excellent performance figures of merit with low area footprint.

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A 0.0053-mm² 6-bit Fully-Standard-Cell-Based Synthesizable SAR ADC in 65 nm CMOS

Cited by 10 publications

References 5 publications

Standard-Cell-Based Comparators for Ultra-Low Voltage Applications: Analysis and Comparisons

Standard-Cell-Based Comparators for Ultra-Low Voltage Applications: Analysis and Comparisons

A High Performance 0.3 V Standard-Cell-Based OTA Suitable for Automatic Layout Flow

A Novel Differential to Single-Ended Converter for Ultra-Low-Voltage Inverter-Based OTAs

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A 0.0053-mm2 6-bit Fully-Standard-Cell-Based Synthesizable SAR ADC in 65 nm CMOS

Cited by 10 publications

References 5 publications

Standard-Cell-Based Comparators for Ultra-Low Voltage Applications: Analysis and Comparisons

Standard-Cell-Based Comparators for Ultra-Low Voltage Applications: Analysis and Comparisons

A High Performance 0.3 V Standard-Cell-Based OTA Suitable for Automatic Layout Flow

A Novel Differential to Single-Ended Converter for Ultra-Low-Voltage Inverter-Based OTAs

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Resources

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A 0.0053-mm² 6-bit Fully-Standard-Cell-Based Synthesizable SAR ADC in 65 nm CMOS