A 0.0027-mm&lt;sup&gt;2&lt;/sup&gt; 9.5-bit 50-MS/s all-digital A/D converter TAD in 65-nm digital CMOS

2010 17th IEEE International Conference on Electronics, Circuits and Systems

Terasawa

2010

Self Cite

An all-digital TAD-OFDM detection method for sensor interface with digital synchronous detection based on TAD (Time AID converter)-type ADC is introduced. A TAD basic structure is a completely digital circuit including a ring delay-line (RDL) with delay units (DUs) driven by an input voltage Vio and an RDL frequency counter, latch and encoder. Since the operating principle is to count the number of DUs through which the delay pulse passes within a sampling period T., this ADC (TAD) naturally performs as a Vio voltage integration circuit for T •. Hence, high frequency noises can be removed simultaneously with AID conversion. First, as an example of a voltage-integration effect as a low-pass tiIter, magnet pick-Up sensing was verified using a 22-bit TAD test chip fabricated using a 0.65-Jlm CMOS with 106 JlV/LSB (100 kS/s). Next, the idea of digital synchronous detection with TAD (called TAD-DSD with the voltage-integration effect) is proposed. Finally, by using the TAD-DSD principle, TAD OFDM detection is presented and experimentally confirmed, resulting in signal-detection of each wave-amplitude from a four-carrier-composite wave, which consists of frequencies, 1.6-, 3.2-, 6.4-and 12.8-MHz, respectively.

Section: Introductionmentioning

confidence: 94%

Section: Tad Operation and Adc Performancementioning

confidence: 99%

All-digital TAD-OFDM detection for sensor interface using TAD-digital synchronous detection

2010 17th IEEE International Conference on Electronics, Circuits and Systems

Terasawa

2010

Self Cite

“…Figure 10 shows TAD's voltage resolution in different CMOS technologies from 0.8 μm to 65 nm [7], including this TAD prototype. It proves that TAD is compatible with CMOS scaling, since voltage resolution is almost perfectly scalable with technology.…”

Section: Measurement Resultsmentioning

confidence: 99%

“…with similar architecture has been demonstrated in 0.8 μm, 0.65 μm, 0.35 μm, 0.18 μm, and 65 nm CMOS. The statistical data of voltage resolution, area and power consumption of these TADs are available in [7], which proves that CMOS scaling can improve TAD's voltage sensitivity. So far, the best voltage resolution of TAD is 15 μV/LSB, achieved at 1 MS/s in 65 nm CMOS process under 1.2 V supply voltage [7].…”

Section: Introductionmentioning

confidence: 90%

An All-Digital Reconfigurable Time-Domain ADC for Low-Voltage Sensor Interface in 65nm CMOS Technology

IEICE Trans. Fundamentals

Miyahara

et al. 2015

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An all-digital time-domain ADC, abbreviated as TAD, is presented in this paper. All-digital structure is intrinsically compatible with the scaling of CMOS technology, and can satisfy the great demand of miniaturized and low-voltage sensor interface. The proposed TAD uses an inverter-based Ring-Delay-Line (RDL) to transform the input signal from voltage domain to time domain. The voltage-modulated time information is then digitized by a composite architecture namely "4-Clock-Edge-Shift Construction" (4CKES). TAD features superior voltage sensitivity and 1storder noise shaping, which can significantly simplify the power-hungry pre-conditioning circuits. Reconfigurable resolution can be easily achieved by applying different sampling rates. A TAD prototype is fabricated in 65 nm CMOS, and consumes a small area of 0.016 mm 2. It achieves a voltage resolution of 82.7 μV/LSB at 10 MS/s and 1.96 μV/LSB at 200 kS/s in a narrow input range of 0.1 Vpp, merely under 0.6 V supply. The highest SNR of TAD prototype is 61.36 dB in 20 kHz bandwidth at 10 MS/s. This paper also analyzes the nonideal effects of TAD and discusses the potential solutions. As the principal drawback, nonlinearity of TAD can be compensated by the differential-setup and digital calibration.

“…As mentioned, a 4CKES TAD architecture [7] is employed to achieve 2-bit higher resolution from the 65nm-TAD original type [8]. A common even-stage RDL and counter are shared by 4 TAD modules (TMs).…”

Section: Introductionmentioning

confidence: 99%

All-digital 0.016mm<sup>2</sup> reconfigurable sensor-ADC using 4CKES-TAD in 65nm digital CMOS

2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)

Miyahara

et al. 2014

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An all-digital reconfigurable (10-to-16-bit) sensor ADC based on TAD (Time A/D converter) is completely digital, using a ring-delay-line RDL driven by an input voltage V in as its power supply. This method realized 16.2bit/100ksps/37.5μW from 0.6V supply without any static current using a 0.016mm 2 prototype 4CKES (4-clock-edge-shift) TAD in a 65nm digital CMOS. Resolutions can be controlled by setting its conversion time T cv . A 13.8bit/1Msps/75.4μW or 10.5bit/10Msps/93.2μW operation is also experimentally confirmed using 0.6V supply. Finally, correction of nonlinearity characteristics has been discussed using differential-setup processing method. I.978-1-4799-4242-8/14/$31.00 c 2014 IEEE