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Behrmann, Gerd; Larsen, Kim Guldstrand; Andersen, Henrik Reif; Hulgaard, Henrik; Lind-Nielsen, Jørn

doi:10.1023/a:1016095519611

Cited by 3 publications

(1 citation statement)

References 9 publications

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“…In [Beh+02], a version of finite state machines called hierarchical state/event machines (HSEMs) is discussed; as explicitly mentioned in [Beh+02], their semantics differ from UML state machines.…”

Section: Criteria For Exclusionmentioning

confidence: 99%

Formalizing UML State Machines for Automated Verification – A Survey

André

Liu

et al. 2023

ACM Comput. Surv.

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The Unified Modeling Language (UML) is a standard for modeling dynamic systems. UML behavioral state machines are used for modeling the dynamic behavior of object-oriented designs. The UML specification, maintained by the Object Management Group (OMG), is documented in natural language (in contrast to formal language). The inherent ambiguity of natural languages may introduce inconsistencies in the resulting state machine model. Formalizing UML state machine specification aims at solving the ambiguity problem and at providing a uniform view to software designers and developers. Such a formalization also aims at providing a foundation for automatic verification of UML state machine models, which can help to find software design vulnerabilities at an early stage and reduce the development cost. We provide here a comprehensive survey of existing work from 1997 to 2021 related to formalizing UML state machine semantics for the purpose of conducting model checking at the design stage.

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Section: Criteria For Exclusionmentioning

confidence: 99%

Formalizing UML State Machines for Automated Verification – A Survey

André

Liu

et al. 2023

ACM Comput. Surv.

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Automated Verification of Executable UML Models

Hansen

Ketema

Luttik

et al. 2011

Formal Methods for Components and Objects

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We present a fully automated approach to verifying safety properties of Executable UML models (xUML). Our tool chain consists of a model transformation program which translates xUML models to the process algebra mCRL2, followed by symbolic model checking using LTSmin. If a safety violation is found, an error trace is visualised as a UML sequence diagram. As a novel feature, our approach allows safety properties to be specified as UML state machines.

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A hierarchical verification approach to verify complex safety control systems based on STAMP

Han

Tang

2019

Science of Computer Programming

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Cited by 3 publications

References 9 publications

Formalizing UML State Machines for Automated Verification – A Survey

Formalizing UML State Machines for Automated Verification – A Survey

Automated Verification of Executable UML Models

A hierarchical verification approach to verify complex safety control systems based on STAMP

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