9.8 An 860μW 2.1-to-2.7GHz all-digital PLL-based frequency modulator with a DTC-assisted snapshot TDC for WPAN (Bluetooth Smart and ZigBee) applications

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

“…The PP-ADPLL also exploits inefficiencies in the conventional phase error processing mechanisms and partitions it in a such a way that the integer part can be disabled after the lock has been achieved, thus further reducing the power consumption. The advantages of the latest PP-ADPLL have been demonstrated by behavioral model simulations and also verified in silicon [15], [16].…”

“…1 (a); and feedback-divider-less counter-based topology [3], [4], [5], [10], [11], [12], [13], [14], [15], [16], as shown in Fig. 1 (b).…”

“…4, is introduced into the AD-PLL [15], [16], [31], [39]. The top two lines show timestamps of the CKV and FREF clock rising edges, respectively, for an example FCW = 2 Fig.…”

A 0.5V 0.5mW switching current source oscillator

“…Lower P DC is typically achieved by scaling up R in =L p ω 0 Q t simply via a large multi-turn inductor [2]. For example, by continuing increasing the inductance by 2× at constant Q t , R in could theoretically enhance by 2×, which would reduce P DC by half with a 3 dB PN degradation.…”

A 0.68V 0.68mW 2.4GHz PLL for ultra-low power RF systems

“…Previous low-voltage PLLs such as [2] and [3] have shown operation down to as low as 0.5V, but the implementations still consume significant power (> 2mW). On the other hand, works such as [4] and [5] demonstrate low power PLLs operating at nominal voltages such as 1V, leaving room for further reduction through voltage scaling. For example, a recent work presented a 0.3V PLL architecture that also has ultra-low 780µW power consumption [6].…”