8-bit 5-MS/s Analog-to-Digital Converter for Pixel-Level Integration

Hansen, Karsten; Reckleben, Christian; Kalavakuru, Pradeep; Szymanski, J. E.; Diehl, I.

doi:10.1109/tns.2013.2280660

Cited by 12 publications

(13 citation statements)

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“…Nevertheless, the offset is not limiting the dynamic range as the ADC can count beyond the 256 th ADU by setting the carry bit (see Section III.B). More details of the ADC working principle and the influence of device parameters and settings are summarized in [25]. Due to time constraints, the evaluation of the camera performance was focused on the gain configurations requested by the first user experiment scheduled to start at SCS on May 29 th , 2019.…”

Section: Experimental Results With the Scs Instrumentmentioning

confidence: 99%

“…IO and power pads are placed on one edge of the ASIC. A detailed description of the ASIC block architecture can be found in the literature [13], [22], [23], [24], [25], [26]. Here we summarize the main characteristics and we focus on the functionalities that determine the performance figures and the operating modes of the overall system.…”

Section: Minisdd Sensorsmentioning

confidence: 99%

“…The implemented Wilkinson type ADC [25], [26] converts the amplitude of the voltage stored on the C S&H into a timing information, thanks to an 8-bit Gray Code Counter (GCC), located at the chip periphery. One ASIC contains 64 GCCs.…”

Section: B Single Slope Adcmentioning

confidence: 99%

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The MiniSDD-Based 1-Mpixel Camera of the DSSC Project for the European XFEL

Porro

Andricek

Castoldi

et al. 2021

IEEE Trans. Nucl. Sci.

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The first DSSC 1-megapixel camera became available at the European XFEL in the Hamburg area in February 2019. It was successfully tested, installed and commissioned at the Spectroscopy and Coherent Scattering Instrument. DSSC is a high-speed, large-area, 2-D imaging detector system optimized for photon science applications in the energy range between 0.25 keV and 6 keV. The camera is based on direct conversion Si-sensors and is composed of 1024×1024 pixels of hexagonal shape with a side length of 136 µm. 256 ASICs provide full parallel readout, comprising analog filtering, digitization and in-pixel data storage. In order to cope with the demanding X-ray pulse time structure of the European XFEL, the DSSC provides a peak frame rate of 4.5 MHz. The first megapixel camera is equipped with Miniaturized Silicon Drift Detector pixel arrays. The intrinsic response of the pixels and the linear readout limit the dynamic range but allow one to achieve noise values of about 60 electrons r.m.s. at the highest frame rate. The challenge of providing high-dynamic range (~10 4 photons/pixel/pulse) and single photon detection simultaneously requires a non-linear system front-end, which will be obtained with the DEPFET active pixel technology foreseen for the advanced version of the camera. This technology will provide lower noise and a nonlinear response at the sensor level. The paper describes the The manuscript was submitted on 28.02.2021. The development described in this work was initiated, funded and coordinated by the European XFEL GmbH in the framework of the DSSC project.

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Section: Experimental Results With the Scs Instrumentmentioning

confidence: 99%

Section: Minisdd Sensorsmentioning

confidence: 99%

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The MiniSDD-Based 1-Mpixel Camera of the DSSC Project for the European XFEL

Porro

Andricek

Castoldi

et al. 2021

IEEE Trans. Nucl. Sci.

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“…For the single-photon resolution, a slope of at least one photon per analog-to-digital converter (ADC) bin is needed. In order to minimize the pixel-error rate, the ADC permits a precise trimming of the gain and offset [4]. The influence of gain and offset errors, as well as noise and differential nonlinearity on the experiment-relevant image fidelity, is treated in [4] and [5].…”

Section: Introductionmentioning

confidence: 99%

“…In order to minimize the pixel-error rate, the ADC permits a precise trimming of the gain and offset [4]. The influence of gain and offset errors, as well as noise and differential nonlinearity on the experiment-relevant image fidelity, is treated in [4] and [5]. The conceptual design of the camera-head electronics was already presented in [6].…”

Section: Introductionmentioning

confidence: 99%

Qualification and Integration Aspects of the DSSC Mega-Pixel X-Ray Imager

Hansen

Klar

Kalavakuru

et al. 2019

IEEE Trans. Nucl. Sci.

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The focal-plane module is the key component of the DEPFET sensor with signal compression (DSSC) mega-pixel X-ray imager and handles the data of 128 × 512 pixels. We report on assembly-related aspects, discuss the experimental investigation of bonding behavior of different adhesives, and present the metrology and electrical test results of the production. The module consists of two silicon (Si) sensors with flip-chip connected CMOS integrated circuits, a Si-heat spreader, a low-temperature co-fired ceramics circuit board, and a molybdenum frame. A low-modulus urethane-film adhesive fills the gaps between onboard components and frame. It is also used between board and heat spreader, reduces the misfit strain, and minimizes the module warpage very efficiently. The heat spreader reduces the on-board temperature gradient by about one order of magnitude. The placement precision of the bare modules to each other and the frame is characterized by a standard deviation below 10 and 65 µm, respectively. The displacement due to the in-plane rotation and vertical tilting errors remains below 80 and 50 µm, respectively. The deflection of the sensor plane shows a mean value below 30 µm with a standard deviation below 15 µm. Less than 4% of the application-specified integrated circuits (ASICs) exhibit a malfunction. More than two-thirds of the sensors have a maximum leakage current below 1 µA.

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