8.3 An 8b DAC-Based SST TX Using Metal Gate Resistors with 1.4pJ/b Efficiency at 112Gb/s PAM-4 and 8-Tap FFE in 7nm CMOS

Kossel, Marcel; Khatri, Vishal; Braendli, Matthias; Francese, Pier Andrea; Morf, Thomas; Yonar, Serdar A.; Prathapan, Mridula; Lukes, E.; Richetta, R.A.; Cox, Carrie

doi:10.1109/isscc42613.2021.9365784

Cited by 23 publications

(4 citation statements)

References 4 publications

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“…From the layout postsimulation results, it could be concluded that the transmitter designed in this paper had good performance and met the design indicators. Table 1 summarizes the performance of this transmitter and compares it with other transmitters with similar rate and process [29][30][31]. It can be found that under the same process, it had a higher eye height and similar performance compared with the advanced 10 nm/7 nm process design.…”

Section: Resultsmentioning

confidence: 98%

A 112 Gb/s DAC-Based Duo-Binary PAM4 Transmitter in 28 nm CMOS

Tang

Shi

et al. 2022

Electronics

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To reduce the high bit error rate of serial transceivers under strong channel attenuation, a low-power 112 Gb/s SerDes transmitter was designed using a duo-binary PAM4 modulation technology. By adopting duo-binary PAM4 modulation technology, the problem of the low bandwidth utilization of a high-speed PAM4 (pulse amplitude modulation 4) signal was improved. The problem of high jitter caused by charge sharing and the limited bandwidth of a 4:1 high-speed MUX was improved by using precharging auxiliary transistors. The system power consumption of the transmitter was reduced by using a 7-bit weighted voltage-driven digital-to-analog converter (DAC). The transmitter was designed with a 28 nm CMOS process and powered by a voltage of 0.9 V. The simulation results showed that when the channel attenuation was 20.9 dB, the transmitter could work at 112 Gb/s, the power consumption was 2.02 pJ/bit, and the linearity was 96.7%.

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Section: Resultsmentioning

confidence: 98%

A 112 Gb/s DAC-Based Duo-Binary PAM4 Transmitter in 28 nm CMOS

Tang

Shi

et al. 2022

Electronics

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“…Because the G m cells always remain active with different tap configurations, driving capability is fully utilized and maximized regardless of required equalization strength at different channel losses. However, for a realistic channel, a reasonable number of bits (usually 6-8 bits) for the DAC is required, which may increase the output parasitics of the G m cells unless careful segmentation technique is taken [4] and degrade the output bandwidth, especially in 28 nm. Moreover, each fully designed G m cell with a serializer, MUX, and driver increases the power overhead due to the added low-speed circuit blocks and capacitive load for the clock distribution.…”

Section: Tx Architecturementioning

confidence: 99%

An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS

Wang

Choi

Lee

et al. 2022

IEEE J. Solid-State Circuits

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This article presents a 200-Gb/s pulse amplitudemodulation four-level (PAM-4) and 100-Gb/s non-return-to-zero (NRZ) transmitter (TX) in 28-nm CMOS technology. To achieve the target data rate, the output bandwidth and swing of the proposed TX are optimized by minimizing the output capacitance of the 4:1 multiplexer (MUX) and driver stage with pull-up current sources and adopting a fully reconfigurable 5-tap feed-forward equalizer (FFE). The key circuit includes a segmented 8:4 MUX and 4:1 MUX/driver, a thermal encoder and retimer, and a flexible clock distribution network. Using the layout generated with Berkeley Analog Generator (BAG), the proposed TX achieves an eye opening with >52.9-mV eye height, 0.36 UI eye width, >98% RLM, and 4.63 pJ/b at 200-Gb/s PAM-4 signaling under >6-dB channel loss at 50 GHz, demonstrating the highest data rate achieved using a planar process.

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“…Therefore, it compensates for the impedance reduction caused by the capacitor. As date rates increase to 56-112 Gb/s, t-coils are widely used [12][13][14][15]. Composed of two coupled inductors, t-coils can achieve better impedance matching and wider bandwidth.…”

Section: Introductionmentioning

confidence: 99%

A Robust LC-π Matching Network for 112 Gb/s PAM4 Receiver in 28 nm CMOS

Han

Zheng

et al. 2023

Electronics

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This article presents analysis, design details, and simulation results of an impedance matching network designed for a 112 Gb/s pulse-amplitude-modulation-4 (PAM4) receiver using an LC-π structure. We designed the bonding wire as a part of the matching network, which reduced design pressure on the equalizer as there will be no need to compensate the loss of the chip package. To avoid robustness issues caused by the fluctuation of the bonding wire inductance, the matching network is designed to bw adjustable by the capacitance on PCB and the terminal resistance. We analyzed the parasitics in the layout and the influence of nearby and dummy metals and obtained reliable simulation results through electromagnetic field simulation. This matching network is designed with a 28 nm CMOS process. Post-layout simulation results show that with bonding wire inductance changing from 150 pH to 250 pH, it can always meet CEI-112G-XSR-PAM4 Extra Short Reach Interface requirements.

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8.3 An 8b DAC-Based SST TX Using Metal Gate Resistors with 1.4pJ/b Efficiency at 112Gb/s PAM-4 and 8-Tap FFE in 7nm CMOS

Cited by 23 publications

References 4 publications

A 112 Gb/s DAC-Based Duo-Binary PAM4 Transmitter in 28 nm CMOS

A 112 Gb/s DAC-Based Duo-Binary PAM4 Transmitter in 28 nm CMOS

An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS

A Robust LC-π Matching Network for 112 Gb/s PAM4 Receiver in 28 nm CMOS

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