8.3 A 3GHz ARM Neoverse N1 CPU in 7nm FinFET for Infrastructure Applications

Christy, R. F.; Riches, Stuart; Kottekkat, Sujil; Gopinath, Prasanth; Sawant, Ketan; Kona, Anitha; Harrison, R.I.

doi:10.1109/isscc19947.2020.9062889

Cited by 10 publications

(6 citation statements)

References 3 publications

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“…The power consumption of the memory controllers, PHY and HBM stacks is 6 Watts per stack (24W for entire chip) based on data sheets for HBM2. For the frequency scaling experiments, we make use of work presented by ARM on their Neoverse N1 CPU, which presents power scaling for 3 GHz to 1.2 GHz [9]. Baseline and Comparing Performance.…”

Section: Methodsmentioning

confidence: 99%

Understanding the Limits of Conventional Hardware Architectures for Deep-Learning

Davies¹,

Labiosa²,

Sankaralingam³

2021

Preprint

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Deep learning and hardware for it has garnered immense academic and industry interest in the past 5 yearsincluding almost 100 startups, more than $5B of VC investment -and a re-relevance of the role of architecture. However, the state-of-art remains NVIDIA's TensorCore-based systems that provide i) top-of-line performance, ii) turnkey software stack, and iii) coverage across a wide-spectrum of DL network styles (DL-architecture in AI parlance). Other academic and industry efforts have included novel approaches like spatial dataflow, CGRAs, systolic arrays, blended FPGA LUTs with fixed function units and more. These have all necessitated their own innovations in architecture, compiler, and software stack integration. However, none of these have yet satisfied all the 3 metrics that NVIDIA's TensorCore and software stack provides, and generally seem to perform worse. In this paper, we systematically investigate the behavior of DL workloads and imputed needs on hardware/compiler/software. We show that SIMD/shortvector, caching, and synchronization in a fairly well-understood multicore chip organization we call UPCYCLE can achieve dayzero software maturity, and provide big integer factor speedups over the state-of-art NVIDIA solutions. Compared to an A100, UPCYCLE at small-batch size is geo-mean 7.7X faster for inference, geo-mean 11.7X faster at training, while consuming only half the power. Second, the UPCYCLE architecture requires no new compiler or software stack innovation. Third, it provides full DL-architecture coverage, and can be instantiated to provide training-optimized, inference-optimized, or balanced training and inference systems. Overall, this paper motivates the treatment of software maturity as a first class design constraint in developing new architectures for DL.

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Section: Methodsmentioning

confidence: 99%

Understanding the Limits of Conventional Hardware Architectures for Deep-Learning

Davies¹,

Labiosa²,

Sankaralingam³

2021

Preprint

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“…Figure 8 shows the SP energy efficiency achieved in a DNN training step overall, and on the compute-bound convolutions specifically, across a variety of networks, and the industry-leading DP efficiency on linear algebra. Manticore's actual efficiency is competitive with the V100 GPU's peak efficiency on DNN training in SP, and it significantly outperforms the peak DP efficiency of Neoverse N1 [3] and Core i9-9900K CPUs, and the V100, even though these chips have a substantial technology advantage due to their 7 nm, 14 nm, and 12 nm FinFET processes, respectively. Manticore delivers significantly higher peak floating-point performance than comparable RISC-V architectures [4] in 16 nm.…”

Section: Applicationsmentioning

confidence: 99%

Manticore: A 4096-Core RISC-V Chiplet Architecture for Ultraefficient Floating-Point Computing

2021

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“…The thermal simulation boundary conditions are calibrated to hardware measurements on a 4-core SoC test chip fabricated on a 7nm process technology [15]. The maxpower workload was run for a fixed number of CPU cycles on all four cores and temperature measurements from on-die temperature sensors were collected.…”

Section: A Model Calibrationmentioning

confidence: 99%

Thermal Analysis of a 3D Stacked High-Performance Commercial Microprocessor using Face-to-Face Wafer Bonding Technology

Mathur

Chao

Liu

et al. 2020

2020 IEEE 70th Electronic Components and Technology Conference (ECTC)

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3D integration technologies are seeing widespread adoption in the semiconductor industry to offset the limitations and slowdown of two-dimensional scaling. High-density 3D integration techniques such as face-to-face wafer bonding with sub-10 µm pitch can enable new ways of designing SoCs using all 3 dimensions, like folding a microprocessor design across multiple 3D tiers. However, overlapping thermal hotspots can be a challenge in such 3D stacked designs due to a general increase in power density. In this work, we perform a thorough thermal simulation study on sign-off quality physical design implementation of a state-of-the-art, high-performance, out-oforder microprocessor on a 7nm process technology. The physical design of the microprocessor is partitioned and implemented in a 2-tier, 3D stacked configuration with logic blocks and memory instances in separate tiers (logic-over-memory 3D). The thermal simulation model was calibrated to temperature measurement data from a high-performance, CPU-based 2D SoC chip fabricated on the same 7nm process technology. Thermal profiles of different 3D configurations under various workload conditions are simulated and compared. We find that stacking microprocessor designs in 3D without considering thermal implications can result in maximum die temperature up to 12°C higher than their 2D counterparts under the worst-case power-indicative workload. This increase in temperature would reduce the amount of time for which a power-intensive workload can be run before throttling is required. However, logic-over-memory partitioned 3D CPU implementation can mitigate this temperature increase by half, which makes the temperature of the 3D design only 6°C higher than the 2D baseline. We conclude that using thermalaware design partitioning and improved cooling techniques can overcome the thermal challenges associated with 3D stacking. This is an accepted version of the IEEE published article presented at IEEE Electronic Components and Technology Conference (ECTC) 2020 http://www.ectc.net.

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8.3 A 3GHz ARM Neoverse N1 CPU in 7nm FinFET for Infrastructure Applications

Cited by 10 publications

References 3 publications

Understanding the Limits of Conventional Hardware Architectures for Deep-Learning

Understanding the Limits of Conventional Hardware Architectures for Deep-Learning

Manticore: A 4096-Core RISC-V Chiplet Architecture for Ultraefficient Floating-Point Computing

Thermal Analysis of a 3D Stacked High-Performance Commercial Microprocessor using Face-to-Face Wafer Bonding Technology

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