74 dB SNDR Multi-Loop Sturdy-MASH Delta-Sigma Modulator Using 35 dB Open-Loop Opamp Gain

Maghari, Nima; Kwon, Sunwoo; Moon, Un-Ku

doi:10.1109/jssc.2009.2022302

Cited by 80 publications

(34 citation statements)

References 16 publications

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“…Table 3 summarizes and compares performance of previously reported low-pass sigma-delta modulators [8][9][10][11][12]. The FoM of reference [8] is better than this design being optimized for a 2 MHz signal band.…”

Section: Resultsmentioning

confidence: 99%

Two op-amps third-order sigma–delta modulator with 61-dB SNDR, 6-MHz bandwidth and 6-mW power consumption

Bonizzoni

Pérez

Maloberti

et al. 2010

Analog Integr Circ Sig Process

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This low-power RD modulator targets the DVB-H requirements and achieves about 10 bit with 6-MHz signal band. Suitable topological modifications enable the realization of a third order modulator with two op-amps. Moreover, a technique for swing reduction of the last op-amp strongly reduces the number of comparators in the quantizer. The power reduction techniques limit the consumption to 6.18 mW, thus yielding a FoM of 0.58 pJ/ conversion. The area of the circuit, fabricated with a 0.18-lm analog CMOS technology, is 0.32 mm 2 . Experimental measurements confirm the behavioral study made accounting for the op-amps limitations.

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Section: Resultsmentioning

confidence: 99%

Two op-amps third-order sigma–delta modulator with 61-dB SNDR, 6-MHz bandwidth and 6-mW power consumption

Bonizzoni

Pérez

Maloberti

et al. 2010

Analog Integr Circ Sig Process

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show abstract

“…Furthermore, the opamp used for the NSIQ can be merged with the active adder to reduce power consumption [4].…”

Section: Smash With Noise-shaped Quantizermentioning

confidence: 99%

“…However, this stability comes with the price of increased sensitivity to analog components such as opamp gain and modulator coefficients [2]. Recently, a new type of multi-loop modulators called Sturdy-MASH (or SMASH), that has been proposed in [3], reduces the sensitivity of the modulator to analog circuit components while providing a decent stability [4]. However, due to the added digital-to-analog converter (DAC) at the input of the modulator (from the output of the second loop), the kT/C noise will increase and also the matching between the DACs will become critical.…”

Section: Introductionmentioning

confidence: 99%

Sturdy-MASH delta-sigma modulator with noise-shaped integrating quantizer and dual-DAC DWA

Han

Kim

Maghari

2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper combines the benefits of the Sturdy-MASH delta-sigma modulator with the benefits of the noiseshaped integrating quantizer. By using the noise-shaped integrating quantizer, the first stage quantization error is directly extracted in time-domain without the need for any extra hardware. This removes the loading on the first loop filter, and allows accurate inter-stage gain scaling. The second loop output is also provided in a time-modulated pulse which operates a DAC at the front-end of the modulator. With the use of dual-DAC data weighted averaging, the mismatch between the front-end DACs is greatly suppressed. Detailed Matlab simulation results are provided to prove the efficiency of the proposed structure.

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“…This modulator loop is chosen for simplicity and any other conventional modulator loop may be used. Single stage NMOS-input opamps with only NMOS cascode transistors are chosen to satisfy the minimum gain requirement of 30 dB and large available output swing [21]. The single-ended implementation is illustrated for simplicity and the actual design uses a fully-differential implementation.…”

Section: Implemented Modulatormentioning

confidence: 99%

A Third-Order DT $\Delta\Sigma$ Modulator Using Noise-Shaped Bi-Directional Single-Slope Quantizer

Maghari

Moon

2011

IEEE J. Solid-State Circuits

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This paper describes a new analog-to-digital converter based on the traditional dual-slope ADC operation. With a small modification to the discharging phase of the dual-slope ADC, first-order quantization noise shaping is achieved. This quantizer is used in a second-order loop filter and results in an overall third-order quantization noise shaping. To remove the need for any extra active element, this quantizer is merged with the active adder. In this fashion, the multi-bit flash ADC is removed and hence the loading of the active-adder is reduced to a single continuous-time comparator. Furthermore, to alleviate the speed of the counting-clock and the common-mode biasing accuracy requirements, a bi-directional discharging scheme is proposed. As a proof of concept, the second-order loop filter with the proposed quantizer is fabricated in a 0.18 m CMOS technology and achieves over 78 dB SNDR with an oversampling ratio of 24 and 50 MHz sampling speed. The power consumption is 2.9 mW from a 1.5 V power supply.

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74 dB SNDR Multi-Loop Sturdy-MASH Delta-Sigma Modulator Using 35 dB Open-Loop Opamp Gain

Cited by 80 publications

References 16 publications

Two op-amps third-order sigma–delta modulator with 61-dB SNDR, 6-MHz bandwidth and 6-mW power consumption

Two op-amps third-order sigma–delta modulator with 61-dB SNDR, 6-MHz bandwidth and 6-mW power consumption

Sturdy-MASH delta-sigma modulator with noise-shaped integrating quantizer and dual-DAC DWA

A Third-Order DT $\Delta\Sigma$ Modulator Using Noise-Shaped Bi-Directional Single-Slope Quantizer

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