70 GSa/s and 51 GHz bandwidth track‐and‐hold amplifier in InP DHBT process

Deza, J.; Ouslimani, A.; Konczykowska, A.; Kasbari, Abed-Elhak; Godin, J.; Pailler, G.

doi:10.1049/el.2013.0271

Cited by 14 publications

(5 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Sampling rate and bandwidth of reported THAs have reached to 40 Gsampling/s and 19 GHz, respectively, for SiGe BiCMOS process, 30 Gsampling/s and 13 GHz, respectively, for CMOS process, 70 Gsampling/s and 51 GHz, respectively, for InP HBT process, 90 Gsampling/s and 19.9 GHz, respectively, for SOI CMOS process during the past 10 years.…”

Section: Introductionmentioning

confidence: 99%

A low sampling clock, high bandwidth, master‐slave track and hold amplifier

Zhang

Zhou

Liu

et al. 2019

Int J RF Microw Comput Aided Eng

View full text Add to dashboard Cite

A fully-differential master-slave track and hold amplifier (MSTHA), with one-input, four-output and nearly 20 GHz bandwidth is designed and fabricated in 0.13-μm SiGe BiCMOS technology. Operating with a single +3.3 V supply, 0 V input directvoltage, 2 GHz sampling clock input and 5 dBm input power, the MSTHA achieves a spurious free dynamic range (SFDR) of less than −31 dB up to 20 GHz, 0.5 mV rms output noise amplitude (RMS, root of mean square) and totally power consumingbandwidth, master-slave, MSTHA, SFDR, SiGe BiCMOS

show abstract

Section: Introductionmentioning

confidence: 99%

A low sampling clock, high bandwidth, master‐slave track and hold amplifier

Zhang

Zhou

Liu

et al. 2019

Int J RF Microw Comput Aided Eng

View full text Add to dashboard Cite

show abstract

“…The InP-based track-and-hold amplifiers [4]- [9] feature state-of-the-art performance, but the cost of the InP process is very high. The SiGe [3], [10]- [13] and CMOS [14]- [18] track-and-hold amplifiers have the advantages of high integration with analog and digital circuits, low voltage, and low cost for mass production.…”

Section: Introductionmentioning

confidence: 99%

“…The input and output buffers are designed to keep input and output waveforms with the same swing. The sample-and-hold stage of the track-and-hold circuit can be designed using a switched emitter follower topology [4], [7]- [9], [11], [13], switched source follower topology [1], [2], switched capacitor technique [15], [16], and self-calibration technique [19]. The switched emitter follower is often designed using the heterojunction bipolar transistor (HBT) in the compound InP or SiGe process to obtain high linearity with high-speed operation, but the dc power consumption is very high to limit for the low-voltage and low-power applications.…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of CMOS High-Speed High Dynamic-Range Track-and-Hold Amplifiers

Liu

Chang

Huang

et al. 2015

IEEE Trans. Microwave Theory Techn.

View full text Add to dashboard Cite

Design and analysis of two high-speed high dynamic-range track-and-hold amplifiers are presented in this paper using 65-and 90-nm CMOS processes. To achieve remarkable circuit performance in the advanced CMOS regime, the cascode topology with an inductive peaking technique and the distributed topology are employed in the track-and-hold amplifiers. The circuit topology is investigated to obtain the design methodology of the CMOS high-speed high dynamic-range track-and-hold amplifier. The theoretical calculation is presented to completely verify the design concept. Moreover, the proposed CMOS track-and-hold amplifiers demonstrate wide bandwidth and good linearity. With a dc power consumption of 197 mW, the 65-nm CMOS track-and-hold amplifier features an input bandwidth of up to 7 GHz, a spurious-free dynamic range (SFDR) of 44.6 dB, and a total harmonic distortion (THD) of 44.5 dB. With a dc power consumption of 216 mW, the 90-nm CMOS track-and-hold amplifier features an input bandwidth of 19 GHz, an SFDR of 47.5 dB, and a THD of 44.5 dB. The proposed CMOS track-and-hold amplifiers are suitable for the high-resolution high-speed analog-to-digital converter with low dc supply voltage and power. Index Terms-CMOS, high-speed analog CMOS design, RF and mixed-signal integrated circuit (IC) design, RF front ends, sampling circuits. 0018-9480Kevin Chen received the M.S. and Ph.D. degrees in electrical and electronic engineering from the University of Bristol, Bristol, U.K., in 2006. He is currently with the Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan, where he was involved in the digital RF receiver design and high-efficiency polar transmitters design. He currently leads an advanced analog and mixed-signal integrated circuit (IC) design team towards the development of high-speed high-resolution analog-to-digital converters (ADCs) and digital-to-analog converters (DACs).

show abstract

“…Recent literature reports InP THA operating up to 70 GS/s [3,4]. Usually, a CMOS ADCs requiring a twochip solution extremely difficult to package while preserving high-speed performance follows the InP THAs.…”

Section: Introductionmentioning

confidence: 99%

A 12-bit track and hold amplifier for giga-sample applications

Cannone

Avitabile

2015

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

The paper presents a track-and-hold amplifier (THA), based on the switched emitter follower topology, suitable for emerging receivers architectures and data acquisition systems. The THA exploits four concurrent techniques, all described in the paper, which allow to reduce the hold-mode feedthrough; to attenuate the differential droop rate; to improve the linearity of the input buffer; and to optimize the third order harmonic distortion for RF sampling operation. The effectiveness of this novel approach is demonstrated using a low cost 0.35 lm SiGe technology. The THA core draws about 145 mA from 3.5 V supply. The THA provides a spurious-free dynamic range (SFDR) better than 72 dB when it is used for sampling an incoming signal of 0.9 V pp centered around 925 MHz at a sampling rate of 0.5 GS/s. The THA allows a max sampling frequency equal to 6 GS/s and a max input frequency equal to 2.5 GHz and provides a SFDR better than 50 dB in all the available working conditions.

show abstract

70 GSa/s and 51 GHz bandwidth track‐and‐hold amplifier in InP DHBT process

Cited by 14 publications

References 4 publications

A low sampling clock, high bandwidth, master‐slave track and hold amplifier

A low sampling clock, high bandwidth, master‐slave track and hold amplifier

Design and Analysis of CMOS High-Speed High Dynamic-Range Track-and-Hold Amplifiers

A 12-bit track and hold amplifier for giga-sample applications

Contact Info

Product

Resources

About