7.5 A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate

Lee, Seungjae; Lee, Jin-Yub; Park, Il-Han; Park, Jongyeol; Sung-Won, Yun; Kim, Minsu; Lee, Jong Hoon; Kim, Minseok; Lee, Kangbin; Kim, Tae‐Eun; Cho, Byung-Kyu; Cho, Dooho; Yun, Sangbum; Im, Jung-No; Yim, Hyejin; Kang, Kyung-Hwa; Jeon, Suchang; Jo, Sungkyu; Ahn, Y. H.; Joe, Sung-Min; Kim, S.; Woo, D. S.; Park, Jiyoon; Park, Hyun-wook; Kim, Young‐Min; Park, Jonghoon; Choi, Yong; Hirano, Makoto; Ihm, Jeong-Don; Jeong, Byunghoon; Lee, Seon-Kyoo; Kim, Moosung; Lee, Ho-Kil; Seo, Sungwhan; Jeon, Hongsoo; Kim, Chanho; Kim, Hyung-Gon; Kim, Jintae; Yim, Yong-Sik; Kim, Hoo-Sung; Byeon, Dae–Seok; Yang, Hyang-Ja; Park, Kitae; Kyung, Kye-Hyun; Choi, Jung Kyu

doi:10.1109/isscc.2016.7417945

Cited by 22 publications

(14 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, the effective cell area, i.e., total chip area divided by the number of cells, is somewhat larger than that because of the overhead circuitry, string contacts with BLs, dummy cells and select transistors. To decrease such overhead, the number of cells in a NAND string has reached the impressive number of 150 in the latest planar nodes [10].…”

Section: Array Architecture and Layoutmentioning

confidence: 99%

“…In NAND arrays, this is achieved via a self-boosting procedure [36], where the inhibited strings are first floated and their potential is temporarily raised via capacitive coupling to the WLs, that are raised at the passing voltage [38]. Program throughput in excess of 50 MB s −1 has been reported [10].…”

Section: Programmentioning

confidence: 99%

“…Such a device was shown to exhibit superior performance with respect to a conventional vertical nanowire transistor, because of the high defectivity in the central region that plagued the performance of the latter structure. The gate stack of today's 3D NAND can be based on either a floating gate [23,[287][288][289][290][291], similar to planar NAND devices, or a charge-trap stack similar to an oxide/nitride/oxide (ONO) layer, where the charge is stored in traps within the nitride layer [10,11,22,292].…”

Section: D Nand Reliabilitymentioning

confidence: 99%

“…The NAND success story is the result of continuous scaling of the planar cell dimensions, that has led all major NAND Flash manufacturers to reach the 15 nm planar node [8][9][10][11]. However, several constraints have severely challenged the latest nodes development [12][13][14], eventually putting an end to the scaling of the planar Flash technology.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

View full text Add to dashboard Cite

Abstract:We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.

show abstract

Section: Array Architecture and Layoutmentioning

confidence: 99%

Section: Programmentioning

confidence: 99%

Section: D Nand Reliabilitymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

View full text Add to dashboard Cite

show abstract

“…MLC [2][3][4] are one of the common and effective schemes to raise storage volume without changing the basic memory array hardware. This method has been extended to triple-level cell (TLC) and quadruple-level cell (QLC) technologies used in many commercial non-volatile memory products [5]. Although this method can greatly enhance memory cell density, storage data integrity is greatly compromised, as a consequence [6][7][8].…”

Section: Introductionmentioning

confidence: 99%

Self-Clamping Programming in Narrow-Bridge Floating Gate Cells for Multi-Level Logic Non-Volatile Memory Applications

Zhuang

Chien

Lin

et al. 2020

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

Memory Applications for the Intelligent Internet of Things

2018

Memories for the Intelligent Internet of Things

View full text Add to dashboard Cite

7.5 A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate

Cited by 22 publications

References 2 publications

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

Self-Clamping Programming in Narrow-Bridge Floating Gate Cells for Multi-Level Logic Non-Volatile Memory Applications

Memory Applications for the Intelligent Internet of Things

Contact Info

Product

Resources

About