7.4: Reduction of Address‐Delay‐Time Degradation by Half‐Pitch Shifted Priming Cell Structure in AC‐PDPs

Abstract

A half‐pitch shifted priming cell structure to reduce address‐delay‐time degradation and lower power consumption has been developed. Discharge transition from a priming cell to a display cell occurred. The time constant of priming electron emission only from the priming cell did not degrade. Observed address‐delay‐time degradation in the display cell reduced.

High‐speed and low‐voltage write addressing of plasma display panels by use of extremely weak discharge

“…For the high‐resolution PDPs, shortening of address period is one of the important subjects to be solved . Therefore, the high‐speed and low‐voltage addressing become more important . The functional material layer for providing electron such as CEL is commonly employed to attain high‐speed and low‐voltage addressing.…”

42.3: New Cell Structure with Priming Cells and Driving Method for High Speed Addressing in AC‐PDPs

“…On the other hand, S. Nobuki et al proposed the Half-Pitch Shifted Priming Cell Structure (HPSPCS) to reduce the address delay time of the initial and after long-term operation [7] [8]. This structure, which gives one solution for high speed addressing without relying on electron emission from MgO, is slightly complicated, and the address delay time depends on the statistical delay time of the priming discharge itself.…”