7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme

Noguchi, Hiroki; Ikegami, Kazutaka; Takaya, Satoshi; Arima, Eishi; Kushida, K.; Kawasumi, A.; Hara, Hiroyuki; Abe, Keiko; Shimomura, N.; Ito, Junichi; Fujita, Shinobu; Nakada, Takashi; Nakamura, Hiroshi

doi:10.1109/isscc.2016.7417942

Cited by 56 publications

(20 citation statements)

References 2 publications

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“…Then, the authors proposed a stochastic circuit design methodology to consider the above errors and demonstrated that such methodology was essential for spintronic logic and memory design [126]. Meanwhile, Toshiba and The University of Tokyo proposed a write-verify-write strategy to improve write reliability in their 4-Mb STT-MRAM prototype [127]. Chen et al [128] exploited STT-MRAM technology to build nonvolatile FPGA for radiation protection.…”

Section: Reliability Solutions From the Circuit Design Perspectivementioning

confidence: 99%

A Survey of Test and Reliability Solutions for Magnetic Random Access Memories

et al. 2021

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| Memories occupy most of the silicon area in nowadays' system-on-chips and contribute to a significant part of system power consumption. Though widely used, nonvolatile Flash memories still suffer from several drawbacks. Magnetic random access memories (MRAMs) have the potential to mitigate most of the Flash shortcomings. Moreover, it is predicted that they could be used for DRAM and SRAM replacement. However, they are prone to manufacturing defects and runtime failures as any other type of memory. This article provides an up-to-date and practical coverage of MRAM test and reliability solutions existing in the literature. After some background on existing MRAM technologies, defectiveness and reliability issues are discussed, as well as functional fault models used for MRAM. This article is dedicated to a summarized description of existing test and reliability improvement methods developed Manuscript

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Section: Reliability Solutions From the Circuit Design Perspectivementioning

confidence: 99%

A Survey of Test and Reliability Solutions for Magnetic Random Access Memories

et al. 2021

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“…Although write-verify-write is a simple scheme, it has been widely adopted in state-of-theart non-volatile memory implementations [41]. While other schemes have been proposed to reduce the number of rewrites to reduce power consumption and improve performance, they are circuit-level optimizations [29].…”

Section: Write Variabilitymentioning

confidence: 99%

A System-Level Simulator for RRAM-Based Neuromorphic Computing Chips

Lee

Cui

Somu

et al. 2018

ACM Trans. Archit. Code Optim.

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Advances in non-volatile resistive switching random access memory (RRAM) have made it a promising memory technology with potential applications in low-power and embedded in-memory computing devices owing to a number of advantages such as low-energy consumption, low area cost and good scaling. There have been proposals to employ RRAM in architecting chips for neuromorphic computing and artificial neural networks where matrix-vector multiplication can be computed in the analog domain in a single timestep. However, it is challenging to employ RRAM devices in neuromorphic chips owing to the non-ideal behavior of RRAM. In this article, we propose a cycle-accurate and scalable system-level simulator that can be used to study the effects of using RRAM devices in neuromorphic computing chips. The simulator models a spatial neuromorphic chip architecture containing many neural cores with RRAM crossbars connected via a Network-on-Chip (NoC). We focus on system-level simulation and demonstrate the effectiveness of our simulator in understanding how non-linear RRAM effects such as stuck-at-faults (SAFs), write variability, and random telegraph noise (RTN) can impact an application's behavior. By using our simulator, we show that RTN and write variability can have adverse effects on an application. Nevertheless, we show that these effects can be mitigated through proper design choices and the implementation of a write-verify scheme. INTRODUCTIONNeuromorphic computing is a domain-specific computing approach that uses analog, digital, or mixed-mode integrated circuits to mimic biological architectures of the neural system, including neurons, axons, synapses, and dendrites [40]. Neurons whose inputs and outputs are spikes are used in neuromorphic computing; the resulting spike-based or spiking neural networks (SNNs) are often regarded as third-generation neural networks [39]. Special-purpose built hardware for neuromorphic computing includes the HiCANN chip [12], NeuroGrid [7], SpiNNaker [9], and IBM's TrueNorth chip [17]. SpiNNaker and TrueNorth are fully digital; HiCANN and NeuroGrid are analog or partially analog in design. In TrueNorth, 4096 neurosynaptic cores of size 256 × 256 are interconnected by an intra-chip network. Using TrueNorth to implement SNNs, Esser et al. demonstrated good accuracies in real-world application benchmarks [22].Concurrent with the developments in neuromorphic computing, advances in non-volatile resistive switching random access memory (RRAM) have made it a suitable memory technology for realizing neuromorphic computing architectures [11]. For instance, RRAM-based neuromorphic computing hardware has been proposed in [19,23,25]. Apart from advantages such as low operating power, high speed and density, memristive and RRAM-based crossbars have been proposed as energy-efficient dot-product engines. These can be used to perform matrix-vector multiplication operations efficiently in the analog domain through current sums [4,6,15]. Such approaches are suitable for low-power embedded devices targeting ne...

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“…Nowadays, smartphones are equipped with the multilevel cache to speed up the application execution time by directly accessing data and instructions from the cache hosted locally. Simulators are used to track memory access pattern for mobile application . However, simulation‐based solutions are offline and computationally very slow.…”

Section: Open Research Issues and Challengesmentioning

confidence: 99%

A survey on energy estimation and power modeling schemes for smartphone applications

Ahmad

Gani

Hamid

et al. 2016

Int J Communication

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In the last decade, the rising trend in the popularity of smartphones motivated software developers to increase application functionality. However, increasing application functionality demands extra power budget that as a result, decreases smartphone battery lifetime. Optimizing energy critical sections of an application creates an opportunity to increase battery lifetime. Smartphone application energy estimation helps investigate energy consumption behavior of an application at diversified granularity (eg, coarse and fine granular) for optimal battery resource use. This study explores energy estimation and modeling schemes to highlight their advantages and shortcomings. It classifies existing smartphone application energy estimation and modeling schemes into 2 categories, ie, code analysis and mobile components power model-based estimation owing to their architectural designs. Moreover, it further classifies code analysis-based modeling and estimation schemes in simulation-based and profiling-based categories. It compares existing energy estimation and modeling schemes based on a set of parameters common in most literature to highlight the commonalities and differences among reported literature. Existing application energy estimation schemes are low-accurate, resource expensive, or non-scalable, as they consider marginally accurate smart battery's voltage/ current sensors, low-rate power capturing tools, and labor-driven lab-setting environment to propose power models for smartphone application energy estimation. Besides, the energy estimation overhead of the components power model-based estimation schemes is very high as they physically run the application on a smartphone for energy profiling. To optimize smartphone application energy estimation, we have highlighted several research issues to help researchers of this domain to understand the problem clearly. KEYWORDS application energy, energy estimation, energy profiling, profiling overhead 1 | INTRODUCTION Nowadays, with the proliferation of portable devices, the energy-efficient system design has become a must-to-meet requirement for recent resource-constrained smartphone devices. The ever growing smartphone user's demands encourage application developers to enrich the legacy applications that as a result, increase smartphone's computational and communication cost. Among all smartphone-based applications, on-demand video, 1 multi-agent-based distributed games, 2 spatial locality-based social applications, 3 pedestrian tracking, 4,5 and context-based advertisement services 6 are the most energy-hungry services. The inherent features of these services considerably increase the energy demands of processors when executed on smartphones. 7-9 It is estimated that in last 2 decades, processor power budget has increased significantly because of smartphone application's high resource use. To efficiently exploit smartphone's power budget, software optimization minimizes inter-component interaction among hardware modules that as a result, increases battery's lifetime. ...

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7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme

Cited by 56 publications

References 2 publications

A Survey of Test and Reliability Solutions for Magnetic Random Access Memories

A Survey of Test and Reliability Solutions for Magnetic Random Access Memories

A System-Level Simulator for RRAM-Based Neuromorphic Computing Chips

A survey on energy estimation and power modeling schemes for smartphone applications

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