65NM sub-threshold 11T-SRAM for ultra low voltage applications

Moradi, Farshad; Wisland, Dag T.; Aunet, Snorre; Mahmoodi, Hamid; Cao, Tuan Vu

doi:10.1109/socc.2008.4641491

Cited by 23 publications

(9 citation statements)

References 10 publications

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“…These solutions span two different dimensions. The first dimension covers designing SRAM bit-cells by up-sizing transistors to achieve higher functionality margins [Liu and Kursun 2007;Moradi et al 2008;Morita et al 2007;Chen et al 2007]. The second dimension covers designing more robust SRAM cells (e.g., Schmitt trigger (ST) SRAM cell [Kulkarni et al 2007]) to ensure improved performance at low fault rates.…”

Section: Circuit-level Solutionsmentioning

confidence: 99%

“…The first category relies on circuit-level techniques that up-size the transistors or implement a more robust SRAM cell (e.g., 8-T or 10-T SRAM cell instead of the traditional 6-T version) [Liu and Kursun 2007;Moradi et al 2008;Morita et al 2007;Chen et al 2007;Maric et al 2013;Kulkarni et al 2007]. This results in an increase in area (33% to 100%) of the SRAM cell, reducing the effective cache capacity within a given area budget.…”

Section: Introductionmentioning

confidence: 99%

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Nuca-L1

Hijaz

Khan

2014

ACM Trans. Archit. Code Optim.

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Research has shown that operating in the near-threshold region is expected to provide up to 10× energy efficiency for future processors. However, reliable operation below a minimum voltage (Vccmin) cannot be guaranteed due to process variations. Because SRAM margins can easily be violated at near-threshold voltages, their bit-cell failure rates are expected to rise steeply. Multicore processors rely on fast private L1 caches to exploit data locality and achieve high performance. In the presence of high bit-cell fault rates, traditionally an L1 cache either sacrifices capacity or incurs additional latency to correct the faults. We observe that L1 cache sensitivity to hit latency offers a design trade-off between capacity and latency. When fault rate is high at extreme Vccmin, it is beneficial to recover L1 cache capacity, even if it comes at the cost of additional latency. However, at low fault rates, the additional constant latency to recover cache capacity degrades performance. With this trade-off in mind, we propose a Non-Uniform Cache Access L1 architecture (NUCA-L1) that avoids additional latency on accesses to fault-free cache lines. To mitigate the capacity bottleneck, it deploys a correction mechanism to recover capacity at the cost of additional latency. Using extensive simulations of a 64-core multicore, we demonstrate that at various bit-cell fault rates, our proposed private NUCA-L1 cache architecture performs better than state-of-the-art schemes, along with a significant reduction in energy consumption. ACM Reference Format:Farrukh Hijaz and Omer Khan. 2014. NUCA-L1: A non-uniform access latency level-1 cache architecture for multicores operating at near-threshold voltages. ACM Trans.

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Section: Circuit-level Solutionsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Nuca-L1

Hijaz

Khan

2014

ACM Trans. Archit. Code Optim.

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“…There have been several efforts at the device level to investigate custom SRAM architectures to improve the reliability of embedded memories, from re-arrangement of the physical-addresses [76], the introduction of customized logic [84], and different cell sizes [17], [53], [72] at the cost of increases in area.…”

Section: B Reliable Memory Subsystemsmentioning

confidence: 99%

Software Controlled Memories for Scalable Many-Core Architectures

Bathen

Dutt

2012

2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications

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Technology scaling along with the ever evolving demand for media-rich software stacks have motivated the need for many-core platforms. With the increase in compute power and its inherent demand for high memory bandwidth comes the need for vast amounts of on-chip memory space. Thus, designers must carefully provision the memory real-estate to meet their application's needs. It has been shown in the embedded systems domain that both software controlled memories (e.g., scratchpad memories) and hardware-controlled memories (e.g., caches) have their pros and cons, some application domains such as multimedia fit very well in the software-controlled memory model, while other domains such as databases work well with caches. As a result, efficient memory management is extremely critical as it has a great impact on the system's power consumption and throughput. Traditional memory hierarchies primarily consist of SRAM-based onchip caches, however, with the emergence of non-volatile memories (NVMs) and mixed-criticality systems, on-chip memories will be heterogeneous, not only in type (cache vs. scratchpad) but also in technology (e.g., SRAM vs. NVM). This paper surveys the state of the art in memory subsystems for many-core platforms, and presents strategies for efficiently managing software-controlled memories in the many-core domain, while addressing the various challenges designers face in deploying such memory subsystems (e.g., sharing the memory resources, accounting for variations in the subsystem, etc.).

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“…Due to the progress of the semiconductor process, the threshold voltage (V TH ) of transistors is decreasing. Smaller V TH leads to bigger leakage current [6,7]. The performance of SRAM would deteriorate as the bit-line leakage increases, and the read operation would even fail when the amount of leakage reaches a critical value [8,9,10,11].…”

Section: Introductionmentioning

confidence: 99%

Additive-calibration scheme for leakage compensation of low voltage SRAM

Peng

Lin

et al. 2016

IEICE Electron. Express

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As the bit-line leakage increases, the performance of SRAM will decline. Especially, the read operation will even fail when the amount of the leakage reaches a critical value. In this paper, we present a new technique, called Additive Calibration (AC), which can combat the bit-line leakage problem even in low voltage. Simulation results show that the maximum tolerant bit-line leakage current of our AC scheme is increased by 45.6% compared with the previous X-calibration scheme. Thus, this method can perform at higher frequency with much lower power consumption.

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65NM sub-threshold 11T-SRAM for ultra low voltage applications

Cited by 23 publications

References 10 publications

Nuca-L1

Nuca-L1

Software Controlled Memories for Scalable Many-Core Architectures

Additive-calibration scheme for leakage compensation of low voltage SRAM

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