63.4: High‐Performance 4K x 2K 65‐in. TV with BCE‐Type Oxide TFTs

et al. 2022

Sci Rep

Amorphous oxide semiconductor (AOS) field-effect transistors (FETs) have been integrated with complementary metal-oxide-semiconductor (CMOS) circuitry in the back end of line (BEOL) CMOS process; they are promising devices creating new and various functionalities. Therefore, it is urgent to understand the physics determining their scalability and establish a physics-based model for a robust device design of AOS BEOL FETs. However, the advantage emphasized to date has been mainly an ultralow leakage current of these devices. A device modeling that comprehensively optimizes the threshold voltage (VT), the short-channel effect (SCE), the subthreshold swing (SS), and the field-effect mobility (µFE) of short-channel AOS FETs has been rarely reported. In this study, the device modeling of two-steps oxygen anneal-based submicron indium-gallium-zinc-oxide (IGZO) BEOL FET enabling short-channel effects suppression is proposed and experimentally demonstrated. Both the process parameters determining the SCE and the device physics related to the SCE are elucidated through our modeling and a technology computer-aided design (TCAD) simulation. In addition, the procedure of extracting the model parameters is concretely supplied. Noticeably, the proposed device model and simulation framework reproduce all of the measured current–voltage (I–V), VT roll-off, and drain-induced barrier lowering (DIBL) characteristics according to the changes in the oxygen (O) partial pressure during the deposition of IGZO film, device structure, and channel length. Moreover, the results of an analysis based on the proposed model and the extracted parameters indicate that the SCE of submicron AOS FETs is effectively suppressed when the locally high oxygen-concentration region is used. Applying the two-step oxygen annealing to the double-gate (DG) FET can form this region, the beneficial effect of which is also proven through experimental results; the immunity to SCE is improved as the O-content controlled according to the partial O pressure during oxygen annealing increases. Furthermore, it is found that the essential factors in the device optimization are the subgap density of states (DOS), the oxygen content-dependent diffusion length of either the oxygen vacancy (VO) or O, and the separation between the top-gate edge and the source-drain contact hole. Our modeling and simulation results make it feasible to comprehensively optimize the device characteristic parameters, such as VT, SCE, SS, and µFE, of the submicron AOS BEOL FETs by independently controlling the lateral profile of the concentrations of VO and O in two-step oxygen anneal process.

Section: Introductionmentioning

confidence: 99%

Device modeling of two-steps oxygen anneal-based submicron InGaZnO back-end-of-line field-effect transistor enabling short-channel effects suppression

et al. 2022

Sci Rep

“…Although amorphous InGaZnO (a‐IGZO) thin‐film transistors (TFTs) have been successfully employed in commercial display products, such as organic light‐emitting diode (OLED) displays and liquid‐crystal displays, the device stability requirement ironically becomes more stringent in future displays with higher resolution, higher frame rate, higher brightness, and longer product lifetime. Precise understanding of the physical origin of degradation mechanism of device instability is really indispensable for oxide TFT‐based displays.…”

Section: Introductionmentioning

confidence: 99%

Experimental decomposition of the positive bias temperature stress-induced instability in self-aligned coplanar InGaZnO thin-film transistors and its modeling based on the multiple stretched-exponential functions

Jang

et al. 2017

Jnl Soc Info Display

Decomposition of the positive gate‐bias temperature stress (PBTS)‐induced instability into contributions of distinct mechanisms is experimentally demonstrated at several temperatures in top‐gate self‐aligned coplanar amorphous InGaZnO thin‐film transistors by combining the stress‐time‐divided measurements and the subgap density‐of‐states (DOS) extraction. It is found that the PBTS‐induced threshold voltage shift (ΔVT) consists of three mechanisms: (1) increase of DOS due to excess oxygen in the active region; (2) shallow; and (3) deep charge trapping in the gate insulator components. Corresponding activation energy is 0.75, 0.4, and 0.9 eV, respectively. The increase of DOS is physically identified as the electron‐capture by peroxide. Proposed decomposition is validated by reproducing the PBTS time‐evolution of I–V characteristics through the technology computer‐aided design simulation into which the extracted DOS and charge trapping are incorporated. It is also found that the quantitative decomposition of PBTS‐induce ΔVT accompanied with the multiple stretched‐exponential models enables an effective assessment of the complex degradation nature of multiple PBTS physical processes occurring simultaneously. Our results can be easily applied universally to any device with any stress conditions, along with guidelines for process optimization efforts toward ultimate PBTS stability.

21‐4: Distinguished Paper: Experimental Decomposition of the Positive Bias Temperature Stress‐induced Instability in Self‐aligned Coplanar InGaZnO Thin‐film Transistors and its Modeling based on the Multiple Stretched‐exponential Functions

Symp Digest of Tech Papers

Jang

et al. 2017

Decomposition of the positive gate‐bias temperature stress (PBTS)‐induced instability into contributions of distinct mechanisms is experimentally demonstrated in top‐gate self‐aligned coplanar amorphous InGaZnO thin‐film transistors and validated by reproducing the PBTS time‐evolution of I‐V characteristics through the TCAD simulation into which the extracted density‐of‐states and charge trapping are incorporated.