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Kittitornkun, Surin; Hu, Yu

doi:10.1023/a:1022028729196

Cited by 3 publications

(2 citation statements)

References 19 publications

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“…This paper presents a modified systolic architecture for the general case of frame-level pipelined FSBM. This modified frame-level pipelined FSBM systolic architecture can do larger search range p=qN, q≥½ while reduces the register amount compared to the unmodified version presented by Kittitornkun, and Hu [1,4] without sacrificing the advantages of using of frame-level FSBM, such as maximizing data re-used. The unmodified architecture, presented in section "FLSA for q≥½" above, requires (2p-N)*(2p)*(2p+1) registers to delay the search data, y 2 .…”

Section: Discussionmentioning

confidence: 99%

“…Kittitornkun and Hu [1,4] proposed a frame-level pipelined systolic array (FLSA) FSBM motion estimation architecture with un-interrupted pipeline operations. It is based on mapping the standard six-level nested Do-loop FSBM algorithm into a two-level nested Do-loop algorithm, and an example design for a small search area, p=N/2, was presented in their paper.…”

Section: Introductionmentioning

confidence: 99%

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A Generalized Frame-Level FSBM FLSA Architecture

Liu¹,

Chien

Hsu

2013

AMM

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Block-based motion estimation plays important roles in video applications such as video compression to detect movements as well as remove temporal redundancies between successive frames. Full-search block-matching (FSBM) is the preferred algorithm for accurate motion estimation. Frame-level pipelined systolic array (FLSA) FSBM architectures have advantages over block-level pipelined architectures in their simpler control and reduced number of memory accesses. In this paper, a frame-level pipelined FSBM motion estimation architecture using array processor for any square, N×N, block size is presented in full detail.

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Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Generalized Frame-Level FSBM FLSA Architecture

Liu¹,

Chien

Hsu

2013

AMM

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A parallelization methodology for reconfigurable systems applied to edge detection

Campos

Cumplido

Feregrino-Uribe³

et al. 2013

2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)

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In this paper, a novel parallelization methodology is applied to Edge Detection Algorithm (EDA). The proposed methodology is based on a multiprojection approach and on a fusion of processor elements. It eliminates the relationship between problem size and processor array size when using methodologies based on projections. EDA is an interesting problem because its data dependencies and its potential parallelism, besides EDA is used in multiple applications. In this study, multiple versions of the EDA architecture are generated in order to fulfill requirements of throughput and implementation area.

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Design of Processor Array Based on an Optimized Multiprojection Approach

Campos¹,

Cumplido²

2012

AECE

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Parallelization methodologies allow to automate the process of designing optimal processor arrays based on mathematical representations of the algorithm to be implemented. In this work, an optimized multiprojection approach based on the Polytope model is proposed as well as an automated way for getting the scheduler and the allocator vectors. Using a recurrence equations representation, three key criteria for choosing the characteristics of the final implementation are also proposed. As a case of study, the methodology is applied on a matrix-vector multiplication example. Results and relevance of the proposed methodology are finally discussed

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Untitled

Cited by 3 publications

References 19 publications

A Generalized Frame-Level FSBM FLSA Architecture

A Generalized Frame-Level FSBM FLSA Architecture

A parallelization methodology for reconfigurable systems applied to edge detection

Design of Processor Array Based on an Optimized Multiprojection Approach

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