622 Mbit/s CMOS limiting amplifier with 40 dB dynamic range

Yoon, Ty; Jalali, Bahram

doi:10.1049/el:19961256

Cited by 8 publications

(1 citation statement)

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“…However, in order to minimize their loading effect on the amplifier and to limit the value of the external capacitors, such resistors cannot have too low a value; resistors of several kiloohms are typically used. A gain stage [7] or an emitter follower [8] are sometimes used in the feedback loop, to provide higher gain or better decoupling. When this topology is used for the offset suppression loop, input matching is typically achieved by adding 50 resistors to ac ground in parallel with the input port of the amplifier [3] as shown in Fig.…”

Section: Analysis Of Passive Offset-cancelling Networkmentioning

confidence: 99%

Input-Matching and Offset-Cancelling Networks for Limiting Amplifiers in Optical Communication Systems

Centurelli¹,

Pallotta

Tommasino

et al. 2006

Analog Integr Circ Sig Process

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The diffusion of optical communication systems in the access network and for short-haul datacom applications requires the use of low-cost plastic packages: the functional block most affected is the limiting amplifier, that is often the first stage of the Clock and Data Recovery (CDR) IC.In this paper we illustrate the design issues of the input-matching and offset-cancelling network for a differential limiting amplifier for optical communication systems, with particular emphasis on the effect of bond wires. We discuss the limitations of passive feedback networks when used both for offset suppression and for input matching, and propose a topology that overcomes such limitations by using an active feedback loop. A 50 -loaded differential pair is used to achieve input matching and high offset suppression, and its buffering action desensitizes the input matching from the effect of the bond wires connecting off-chip filtering capacitors. Very good performance even with low cost plastic packages can be achieved by solving the trade-off between power consumption, offset suppression and the value of the low-pass filtering capacitors.Design examples of CDR IC's for 2.5 Gb/s optical systems are presented to compare the proposed topology with solutions based on passive feedback networks.

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Section: Analysis Of Passive Offset-cancelling Networkmentioning

confidence: 99%