6.9 A 1.1µm 33Mpixel 240fps 3D-stacked CMOS image sensor with 3-stage cyclic-based analog-to-digital converters

Arai, Toshiki; Yasue, Toshio; Kitamura, Keiichi; Shimamoto, Hiroshi; Kosugi, Tadayoshi; Jun, Sung-Wook; Aoyama, Satoshi; Ming-Chieh, Hsu; Yamashita, Y.; Sumi, Hirofumi; Kawahito, Shoji

doi:10.1109/isscc.2016.7417939

Cited by 29 publications

(15 citation statements)

References 4 publications

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“…As a consequence, the image produced by the image sensor is chopped. The same effect is also noticed in the topologies discussed in [1, 2 ]. Another topology, which has been proposed in [3 ], is depicted in Fig.…”

Section: Introductionsupporting

confidence: 75%

Pipelined extended‐counting for 3D‐stacked CMOS image sensors

2020

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A novel multi-stage pipelined extended-counting (EC) IDS for 3D-stacked CMOS image sensors is presented, which combines the benefits of a pipelined ADC, a first-order IDS ADC and the EC principle in order to simultaneously achieve a high resolution and a high frame rate for 3D-stacked imagers. By assigning each stage of the pipeline to a sub-column of pixels while choosing another input stage of the pipeline when a sub-column has been read out, discontinuous rolling shutter artefacts like chopped images can be eliminated and frame rates up to 340 fps can be achieved for imagers with 8 K resolution.

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Section: Introductionsupporting

confidence: 75%

Pipelined extended‐counting for 3D‐stacked CMOS image sensors

2020

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“…O Because CMOS image sensor has the characteristics of high integration, low power consumption and fast speed, the demand for CMOS image sensor is growing rapidly with the increasing application in recent years. At the same time, BSI and 3D stacked CMOS image sensors have high sensitivity and integration for small pixels [6][7][8][9][10][11], which make up for the shortcomings of CCD and will further expand its application scope.…”

Section: Introductionmentioning

confidence: 99%

An improved segmented DAC for column readout circuit correction of large array CMOS image sensor

Guo

2020

IEICE Electron. Express

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The non-ideal factors and error sources of segmented DAC for multi-channel large array CMOS image sensor are given. An improved precise segmented DAC using adaptive switching technology is proposed. This scheme has been verified on a 50mm×50mm large array CMOS image sensor prototype chip, which consisting of 8320× 8320 pixel array was designed and fabricated in 55nm CMOS 1P4M standard process. The measurement results show that the DNL of DAC can be reduced from 33 LSBs of traditional structure to within 0.5LSB, and the large array sensor chip reaches a high intrinsic dynamic range of 75dB, a low FPN of 0.06%, and a low photo response nonuniformity of 1.5% respectively. Finally, a good raw image is taken by the prototype sensor.

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“…Currently, high-resolution and high reality cameras are required for use in broadcasting, security, automotive, and various other systems. Moreover, 8K digital cameras or 8K video cameras for ultra-high-definition television (UHD TV) systems have been developed [1,2,3,4,5,6]. The International Telecommunication Union (ITU)-R has standardized video parameters for UHD TV as 7680 (H) × 4320 (V) pixels, 120 Hz frame frequency, etc.…”

Section: Introductionmentioning

confidence: 99%

“…[1]. To meet these specifications, 8K or higher resolution complementary metal-oxide-semiconductor (CMOS) image sensors with high-speed and a high saturation signal have been developed [2,3,4,5,6]. Furthermore, the 8K resolution cameras can be adapted for mobile phones that have a sensor size limitation.…”

Section: Introductionmentioning

confidence: 99%

Front-Inner Lens for High Sensitivity of CMOS Image Sensors

Seok

Kim

2019

Sensors

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Due to the continuing improvements in camera technology, a high-resolution CMOS image sensor is required. However, a high-resolution camera requires that the pixel pitch is smaller than 1.0 μm in the limited sensor area. Accordingly, the optical performance of the pixel deteriorates with the aspect ratio. If the pixel depth is shallow, the aspect ratio is enhanced. Also, optical performance can improve if the sensitivity in the long wavelengths is guaranteed. In this current work, we propose a front-inner lens structure that enhances the sensitivity to the small pixel size and the shallow pixel depth. The front-inner lens was located on the front side of the backside illuminated pixel for enhancement of the absorption. The proposed structures in the 1.0 μm pixel pitch were investigated with 3D optical simulation. The pixel depths were 3.0, 2.0, and 1.0 μm. The materials of the front-inner lens were varied, including air and magnesium fluoride (MgF2). For analysis of the sensitivity enhancement, we compared the typical pixel with the suggested pixel and confirmed that the absorption rate of the suggested pixel was improved by a maximum of 7.27%, 10.47%, and 29.28% for 3.0, 2.0, and 1.0 μm pixel depths, respectively.

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6.9 A 1.1µm 33Mpixel 240fps 3D-stacked CMOS image sensor with 3-stage cyclic-based analog-to-digital converters

Cited by 29 publications

References 4 publications

Pipelined extended‐counting for 3D‐stacked CMOS image sensors

Pipelined extended‐counting for 3D‐stacked CMOS image sensors

An improved segmented DAC for column readout circuit correction of large array CMOS image sensor

Front-Inner Lens for High Sensitivity of CMOS Image Sensors

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