2019 IEEE International Solid- State Circuits Conference - (ISSCC) 2019
DOI: 10.1109/isscc.2019.8662361
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6.7 A 112Gb/s PAM-4 Voltage-Mode Transmitter with 4-Tap Two-Step FFE and Automatic Phase Alignment Techniques in 40nm CMOS

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Cited by 17 publications
(2 citation statements)
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“…Introduction: In recent years, the demand of mass data transmission has been pushing the data rate up rapidly. In the summit of '2019 IEEE International Solid-State Circuits Conference (ISSCC)', some research on 100 Gb/s node transmitter [1,2] and receiver [3] were published. With the rapid growth of data rate, the development of transceiver faces some challenges.…”
mentioning
confidence: 99%
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“…Introduction: In recent years, the demand of mass data transmission has been pushing the data rate up rapidly. In the summit of '2019 IEEE International Solid-State Circuits Conference (ISSCC)', some research on 100 Gb/s node transmitter [1,2] and receiver [3] were published. With the rapid growth of data rate, the development of transceiver faces some challenges.…”
mentioning
confidence: 99%
“…Assuming the current state is S 1 (e.g. ab, cd, ef, gh), the number of states that may serve as its next state (N next for S1 ) is 60, calculated as (2). Then, the number of mappings between coded data and original data (N mapping for S1 ) is 1440, calculated as (3), which means that eight channels can transmit 10-bit data…”
mentioning
confidence: 99%