6.1 A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET

Cevrero, Alessandro; Özkaya, İlter; Francese, Pier Andrea; Brändli, Matthias; Menolfi, Christian; Morf, Thomas; Kossel, Marcel; Kull, Lukas; Luu, Danny; Dazzi, Martino; Toifl, Thomas

doi:10.1109/isscc.2019.8662495

Cited by 44 publications

(24 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Today, 100 Gb/s communication per channel is achieved using digital pre-equalizers and DAC at the transmitter [3] and a combination of CTLE, ADC, and digital equalizer at the receiver. This data rate is achieved in conjunction with PAM-4 modulation [1] and in combination with partial response signaling [4]. However, a question still remains as to how far we can push the data rate without sacrificing the bit error rate for a given channel and its impairments.…”

Section: Introductionmentioning

confidence: 99%

Performance Comparison of Baseband Signaling and Discrete Multi-Tone for Wireline Communication

Salinas

Cosson-Martin

Laghaei

et al. 2021

IEEE Open J. Circuits Syst.

View full text Add to dashboard Cite

Limits of data rate over a wireline channel depend on the channel characteristics, the signaling or modulation scheme, and the complexity one can afford for its implementation. This article compares two signaling schemes, namely baseband and discrete multi-tone (DMT), for two example channels, one with a smooth frequency response and one with a notch frequency response, to examine how far each can push the data rate towards the maximum achievable data rate, derived from Shannon Capacity formula. INDEX TERMS Discrete multi-tone (DMT), pulse amplitude modulation (PAM), quadrature amplitude modulation (QAM), Shannon's capacity, bit loading, salz SNR, integrated crosstalk noise (ICN), insertion loss (IL).

show abstract

Section: Introductionmentioning

confidence: 99%

Performance Comparison of Baseband Signaling and Discrete Multi-Tone for Wireline Communication

Salinas

Cosson-Martin

Laghaei

et al. 2021

IEEE Open J. Circuits Syst.

View full text Add to dashboard Cite

show abstract

“…On the other hand, the DFE does not suffer from noise amplification but can only remove post-cursor ISIs. Moreover, alleviating the critical timing path in the DFE feedback loop requires parallelization, which generally limits the DFE to only 1-2 taps in 100Gb/s+ wireline applications [1][2]. FFE and DFE tap coefficients are typically optimized to maximize signal-to-noise ratio (SNR) or to minimize the mean-squared error (MMSE) or pre-FEC BER [3][4][5].…”

Section: Introductionmentioning

confidence: 99%

Pre-FEC and Post-FEC BER as Criteria for Optimizing Wireline Transceivers

Yang

Shahramian

Wong

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

Forward-error-correction (FEC) codes have become an integral part of high-speed wireline links. Signal-to-noise ratio, minimum mean-squared error, and pre-FEC BER are common performance metrics used to design and optimize link parameters, such as the tap coefficients in feed-forward and decision-feedback equalizers. This paper shows that the equalizer parameters found by conventional methods do not necessarily minimize post-FEC BER due to the unaccounted-for negative impact of DFE error propagation on FEC performance. However, the introduction of 1/(1+D) pre-coding eliminates long error bursts so that both pre-FEC and post-FEC BER are minimized with the same equalizer coefficients. These observations may have implications on the architecture and optimization of wireline transceivers.

show abstract

“…TX adaptation can enable higher data rates while keeping power low. For example, accurately setting the TX equalizer in [4] allowed the use of a simplified and very low-power RX architecture in [5]. To facilitate this, a secondary communication link, i.e., a backchannel, would be required to permit the RX to transmit control bits embedding information, such as ISI, channel response, BER, process variation, and temperature back to the TX.…”

Section: Introductionmentioning

confidence: 99%

Secondary Side-Channel Wireline Communication Using Transmitter Clock Frequency Modulation

Zhang

Liang

Shahramian

et al. 2020

IEEE Solid-State Circuits Lett.

View full text Add to dashboard Cite

A secondary communication link, or side-channel, is proposed, which uses binary frequency shift keying to modulate the frequency of a high-speed wireline transmitter clock. This side-channel data is then received using the corresponding receiver's conventional clock and data recovery (CDR) circuit. An analysis of the CDR loop parameters demonstrates that, within certain limits, the side-channel does not impact the signal integrity of the primary high-speed data. Measurements were made on a side-channel prototype using a 56-Gb/s PAM-4 (half-rate 14-GHz clock) transceiver in 7-nm FinFET technology through a 15-dB loss channel. Over 10 4 side-channel bits were transmitted at 50 kb/s, and the side-channel remained error-free with no visible impact on the high-speed link.

show abstract

6.1 A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET

Cited by 44 publications

References 2 publications

Performance Comparison of Baseband Signaling and Discrete Multi-Tone for Wireline Communication

Performance Comparison of Baseband Signaling and Discrete Multi-Tone for Wireline Communication

Pre-FEC and Post-FEC BER as Criteria for Optimizing Wireline Transceivers

Secondary Side-Channel Wireline Communication Using Transmitter Clock Frequency Modulation

Contact Info

Product

Resources

About