59.9 mV·dec Subthreshold Swing Achieved in Zinc Tin Oxide TFTs With In Situ Atomic Layer Deposited AlO Gate Insulator<sup />
                  <sub />
                  <sub />

Newsom, Tonglin L.; Allemang, Christopher; Cho, Tae H.; Dasgupta, Neil P.; Peterson, Robert A.

doi:10.1109/led.2022.3219351

Cited by 8 publications

(7 citation statements)

References 34 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Thus, D n would also be a gate-bias-dependent factor for disordered semiconductors, which can be termed as D n (V gs ). As a result, the subthreshold current for disordered semiconductors can be generally expressed as in Equation (8). In this study, for simplicity, we assume the factors can be expressed as gate-bias-dependent power laws as in Equation ( 9), of which the subthreshold current relation can be given by Equation (10), where V fb is the flatband voltage of the ZnO TFTs.…”

Section: Resultsmentioning

confidence: 99%

“…Especially the subthreshold voltage operation of oxide-based TFTs has been an emerging technology for low-power applications [ 5 ]. Hence, efforts to achieve steep-subthreshold-swing oxide TFTs have led to several proposed approaches, such as applying Schottky source/drain contacts [ 6 ], implementing a high- K dielectric such as HfO 2 [ 7 ], and depositing an in situ Al 2 O 3 gate insulator [ 8 ]. Although there has been progress, the observed steep subthreshold swings were generally minimally extracted values, thereby rendering their application to the devices.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Subthreshold Conduction of Disordered ZnO-Based Thin-Film Transistors

Yoon

2023

Micromachines

View full text Add to dashboard Cite

This study presents the disorderedness effects on the subthreshold characteristics of atomically deposited ZnO thin-film transistors (TFTs). Bottom-gate ZnO TFTs show n-type enhancement-mode transfer characteristics but a gate-voltage-dependent, degradable subthreshold swing. The charge-transport characteristics of the disordered semiconductor TFTs are severely affected by the localized trap states. Thus, we posit that the disorderedness factors, which are the interface trap capacitance and the diffusion coefficient of electrons, would result in the degradation. Considering the factors as gate-dependent power laws, we derive the subthreshold current–voltage relationship for disordered semiconductors. Notably, the gate-dependent disorderedness parameters are successfully deduced and consistent with those obtained by the gm/Ids method, which was for the FinFETs. In addition, temperature-dependent current–voltage analyses reveal that the gate-dependent interface traps limit the subthreshold conduction, leading to the diffusion current. Thus, we conclude that the disorderedness factors of the ZnO films lead to the indefinable subthreshold swing of the ZnO TFTs.

show abstract

Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Subthreshold Conduction of Disordered ZnO-Based Thin-Film Transistors

Yoon

2023

Micromachines

View full text Add to dashboard Cite

show abstract

“…However, a dramatic increase in gate leakage current density would occur when downscaling the physical thickness of SiO 2 due to a considerable tunneling probability. To address this issue, high dielectricconstant (high-k) insulating layers, such as aluminum oxide (Al 2 O 3 ), [11][12][13] hafnium oxide (HfO 2 ), [14][15][16] and zirconium oxide (ZrO 2 ), [17][18][19] have been proposed and implemented within the realm of TFTs. The higher k values of these gatedielectric layers allow to achieve the desired gate capacitances and reasonable gate leakage simultaneously since their large physical thicknesses are able to suppress the tunneling rate.…”

Section: Introductionmentioning

confidence: 99%

“…The higher k values of these gatedielectric layers allow to achieve the desired gate capacitances and reasonable gate leakage simultaneously since their large physical thicknesses are able to suppress the tunneling rate. [11][12][13][14][15][16][17][18][19] We have reported a novel scheme 20) stemming from a onemask film-profile engineering (FPE) technique 21,22) for the fabrication of OS-TFTs with the bottom-gated (BG) configuration. In this proposed FPE approach, a suspended inorganic (e.g.…”

Section: Introductionmentioning

confidence: 99%

A low-temperature photoresist-based film-profile engineering scheme for fabricating bottom- and double-gated indium–gallium–zinc oxide TFTs

Liu,

Lin,

Chen

et al. 2024

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

We proposed a novel low-temperature (<110 oC) process scheme based on the film-profile engineering (FPE) technique for fabricating indium-gallium-zinc oxide (IGZO) thin-film transistors (TFTs) with both bottom-gated (BG) and double-gated (DG) configurations. An organic photoresist (PR) suspended bridge is constructed to shadow the depositing species during the deposition processes of the bottom gate-oxide, channel, and source/drain metal films. An Al2O3 layer deposited at 110 °C using atomic-layer deposition (ALD) is employed as the bottom gate-oxide layer. Such a low-temperature process allows us to deposit the Al2O3 layer following the formation of the PR suspended bridge, preventing the formation of organic residues between the gate-oxide and channel layers. As a result, excellent device performance in terms of field-effect mobility of 12.1 cm²/V-s and subthreshold swing of 141 mV/dec is achieved. Our proposed low-temperature process scheme is readily applicable for fabricating DG TFTs which show substantial enhancements in driving currents.

show abstract

“…This high SS value can be attributed to the high density of Al 2 O 3 / Ga 2 O 3 interface trap states. The upper limit of the interface trap state density can be estimated using the following equation: 4,20…”

mentioning

confidence: 99%

Monolithic β -Ga2O3 NMOS IC based on heteroepitaxial E-mode MOSFETs

Khandelwal

Yuvaraja

garcia

et al. 2023

Applied Physics Letters

View full text Add to dashboard Cite

In this Letter, we report on a monolithically integrated β-Ga2O3 NMOS inverter integrated circuit (IC) based on heteroepitaxial enhancement mode (E-mode) β-Ga2O3 metal-oxide-semiconductor field-effect transistors on low-cost sapphire substrates. A gate recess technique was employed to deplete the channel for E-mode operation. The E-mode devices showed an on-off ratio of ∼105 with a threshold voltage of 3 V. In comparison, control devices without the gate recess exhibited a depletion mode (D-mode) with a threshold voltage of [Formula: see text]3.8 V. Furthermore, depletion-load NMOS inverter ICs were fabricated by monolithically integrating D- and E-mode transistors on the same substrate. These NMOS ICs demonstrated inverter logic operation with a voltage gain of 2.5 at VDD = 9 V, comparable with recent GaN and other wide-bandgap semiconductor-based inverters. This work lays the foundation for heteroepitaxial low-cost and scalable β-Ga2O3 ICs for monolithic integration with (ultra)wide bandgap Ga2O3 power devices.

show abstract

59.9 mV·dec Subthreshold Swing Achieved in Zinc Tin Oxide TFTs With In Situ Atomic Layer Deposited AlO Gate Insulator

Cited by 8 publications

References 34 publications

Subthreshold Conduction of Disordered ZnO-Based Thin-Film Transistors

Subthreshold Conduction of Disordered ZnO-Based Thin-Film Transistors

A low-temperature photoresist-based film-profile engineering scheme for fabricating bottom- and double-gated indium–gallium–zinc oxide TFTs

Monolithic β -Ga2O3 NMOS IC based on heteroepitaxial E-mode MOSFETs

Contact Info

Product

Resources

About