50 nm Vertical Replacement-Gate (VRG) pMOSFETs

Oh, Sang‐Hyun; Hergenrother, J. M.; Nigam, T.; Monroe, Don; Klemens, F.; Kornblit, A.; Mansfield, William; Baker, Matthew R.; Barr, D.; Baumann, F.H.; Bolan, K.; Boone, T.; Ciampa, N.A.; Cirelli, Raymond A.; Eaglesham, D. J.; Ferry, E.; Fiory, A. T.; Frackoviak, J.; Garno, J. P.; Gossmann, H.‐J.; Grazul, John; Green, M.L.; Hillenius, S.J.; Johnson, Richard W.; Keller, Robert C.; King, C.; Kleiman, R. N.; Lee, J.T.-C.; Miner, J.F.; Morris, M.D.; Rafferty, C. S.; Rosamilia, J. M.; Short, K. T.; Sorsch, T.; Timko, Allen G.; Weber, Gary R.; Wilk, G. D.; Plummer, J.D.

doi:10.1109/iedm.2000.904260

Cited by 2 publications

(6 citation statements)

References 7 publications

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“…It is also good for vGAAFETs to use high mobility materials for their channels, which usually have small carrier effective masses and large tunneling leakage current, since relatively long gate length could be applied. Several fabrication methods for vGAAFETs were proposed, including bottom-up [38][39][40][41][42] and top-down [43][44][45][46] based on the ways to form vertical device channels. TEM cross-section for a Si channel vGAAFET with channel-last bottom-up method is shown in Figure 2 [38].…”

Section: Introductionmentioning

confidence: 99%

“…This process is also compatible with the scheme of replacement metal gate. However, when the diameter of the channel hole becomes smaller and the aspect ratio becomes larger, especially for vertically stacked multi-device-layer Several fabrication methods for vGAAFETs were proposed, including bottom-up [38][39][40][41][42] and top-down [43][44][45][46] based on the ways to form vertical device channels. TEM cross-section for a Si channel vGAAFET with channel-last bottom-up method is shown in Figure 2 [38].…”

Section: Introductionmentioning

confidence: 99%

“…However, when the diameter of the channel hole becomes smaller and the aspect ratio becomes larger, especially for vertically stacked multi-device-layer Several fabrication methods for vGAAFETs were proposed, including bottom-up [38][39][40][41][42] and top-down [43][44][45][46] based on the ways to form vertical device channels. TEM cross-section for a Si channel vGAAFET with channel-last bottom-up method is shown in Figure 2 [38]. The method concerns forming bottom borosilicate glass (BSG), gate layer, and top BSG layers at first, and then etching channel holes through these layers stopping on the bottom Si.…”

Section: Introductionmentioning

confidence: 99%

“…The transfer and output characteristics of an InAs vGAAFET consisting of 280 nanowires in parallel Figure 2. TEM cross-section of a Si channel vertical GAAFET (vGAAFET) with channel last or growth from bottom to top after the formation of bottom bottom borosilicate glass (BSG), gate layer, and top BSG layers [38].…”

Section: Introductionmentioning

confidence: 99%

“…Top-down methods are employed to make vGAAFETs with the better reproducibility and less defectivity than bottom-up. For instances, the size of nanowires can be well defined by lithography while the channel can be formed on entire wafers [45] or high-quality films [31] instead of growth with small catalyst caps [41,55] or through small channel holes [38]. Figure 6 (a) shows an InGaAs nanosheet FET made by top-down method [45].…”

Section: Introductionmentioning

confidence: 99%

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State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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New structure transistors for advanced technology node CMOS ICs

Zhang,

Luo

et al. 2024

National Science Review

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Over recent decades, advancements in complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) have mainly relied on structural innovations in transistors. From planar transistors to the fin field-effect transistor (FinFET) and gate-all-around FET (GAAFET), more gate electrodes have been added to 3D channels with enhanced control and carrier conductance to provide higher electrostatic integrity and higher operating currents within the same device footprint. Beyond the 1-nm node, Moore’s law scaling is no longer expected to be applicable to geometrical shrinkage. Vertical transistor stacking, e.g. in complementary FETs (CFETs), 3D stack (3DS)-FETs and vertical-channel transistors, for enhanced density and variable circuit or system design represents a revolutionary scaling approach for sustained IC development. Herein, innovative works on specific structures, key process breakthroughs, shrinking cell sizes, and design methodologies for transistor structure research and development are reviewed. Perspectives on future innovations in advanced transistors with new channel materials and operating theories are also discussed.

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50 nm Vertical Replacement-Gate (VRG) pMOSFETs

Cited by 2 publications

References 7 publications

State of the Art and Future Perspectives in Advanced CMOS Technology

State of the Art and Future Perspectives in Advanced CMOS Technology

New structure transistors for advanced technology node CMOS ICs

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