50-nm self-aligned-gate pseudomorphic AlInAs/GaInAs high electron mobility transistors

Nguyen, L.D.; Brown, April S.; Thompson, M. A.; Jelloian, L.M.

doi:10.1109/16.155871

Cited by 397 publications

(69 citation statements)

References 21 publications

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“…In the compound semiconductor FETs and HEMTs, Schottky junction has been used as the gate structure for a long time, and a cutoff frequency of GHz was obtained in 2001 [1]. However, the progress in the cutoff frequency is very slow (from GHz [2] in 1992 to 396 GHz in 2001) because of short-channel effects (SCEs). In the Schottky gate structure, the gate leakage current increases due to tunneling effect according to an increase of the donor density which accompanies with downsizing the device to achieve high-speed operation.…”

mentioning

confidence: 99%

Fabrication of GaAs MISFET with nm-thin oxidized layer formed by UV and ozone process

Iiyama

Kita

Ohta

et al. 2002

IEEE Trans. Electron Devices

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Abstract-A gate insulating layer with single nm-order thickness for suppressing gate leakage current is one of the key factors in extending downsizing limits, based upon the scaling rule, of field-effect-type transistors. We describe the fabrication and characterization of GaAs MISFETs with a nm-thin oxidized layer as the gate insulating layer, which is formed by an ultraviolet (UV) and ozone process. The UV and ozone process forms oxidized GaAs layers near the surface, which effectively suppress the reverse leakage current by several orders of magnitude. The fabricated GaAs MISFET can operate not only in the depletion mode, but also in the accumulation mode up to 3 V of the gate voltage for 8-nm-thick oxidized layer due to the current blocking effect of the oxidized layer. A current cutoff frequency of 6 GHz and a maximum oscillation frequency of 8 GHz are obtained for a GaAs MISFET with a 1-m-long gate length and 8-nm-thick oxidized layer.Index Terms-Compound semiconductors, GaAs, MISFET, selfalign, ultraviolet (UV) and ozone process.

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mentioning

confidence: 99%

Fabrication of GaAs MISFET with nm-thin oxidized layer formed by UV and ozone process

Iiyama

Kita

Ohta

et al. 2002

IEEE Trans. Electron Devices

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“…The data show no apparent difference in the mobility and density for samples with and without the GaAs buffer layer. As 25,26 To test the importance of the growth temperature, d-doping substrate temperatures of 430°C, 470°C, and 500°C were also used. As shown in Table I, there is no significant effect on the mobility or density.…”

Section: Resultsmentioning

confidence: 99%

InAlSb/InAs/AlGaSb Quantum Well Heterostructures for High-Electron-Mobility Transistors

Bennett

Boos

Ancona

et al. 2007

Journal of Elec Materi

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Heterostructures for InAs-channel high-electron-mobility transistors (HEMTs) were investigated. Reactive AlSb buffer and barrier layers were replaced by more stable Al 0.7 Ga 0.3 Sb and In 0.2 Al 0.8 Sb alloys. The distance between the gate and the channel was reduced to 7-13 nm to allow good aspect ratios for very short gate lengths. In addition, n + -InAs caps were successfully deposited on the In 0.2 Al 0.8 Sb upper barrier allowing for low sheet resistance with relatively low sheet carrier density in the channel. These advances are expected to result in InAs-channel HEMTs with enhanced microwave performance and better reliability.

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“…The self-aligned T-gate process, successfully adopted into a short gate length HEMT process by Nguyen et al [5], allows for a reduction in the device access resistance by reducing the physical separation between the metallized ohmic contacts and the intrinsic gate region. Conversely, by bringing the ohmic contacts in closer proximity to the gate, the magnitude of the gate fringing capacitance will be larger with the self-aligned architecture than with a "standard" device geometry.…”

Section: Introductionmentioning

confidence: 99%

50-nm Self-Aligned and “Standard” T-gate InP pHEMT Comparison: The Influence of Parasitics on Performance at the 50-nm Node

Moran

McLelland

Elgaid

et al. 2006

IEEE Trans. Electron Devices

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Abstract-Continued research into the development of III-V high-electron mobility transistors (HEMTs), specifically the minimization of the device gate length, has yielded the fastest performance reported for any three terminal devices to date. In addition, more recent research has begun to focus on reducing the parasitic device elements such as access resistance and gate fringing capacitance, which become crucial for short gate length device performance maximization. Adopting a self-aligned T-gate architecture is one method used to reduce parasitic device access resistance, but at the cost of increasing parasitic gate fringing capacitances. As the device gate length is then reduced, the benefits of the self-aligned gate process come into question, as at these ultrashort-gate dimensions, the magnitude of the static fringing capacitances will have a greater impact on performance. To better understand the influence of these issues on the dc and RF performance of short gate length InP pHEMTs, the authors present a comparison between In 0.7 Ga 0.3 As channel 50-nm selfaligned and "standard" T-gate devices. Figures of merit for these devices include transconductance greater than 1.9 S/mm, drive current in the range 1.4 A/mm, and f T up to 490 GHz. Simulation of the parasitic capacitances associated with the self-aligned gate structure then leads a discussion concerning the realistic benefits of incorporating the self-aligned gate process into a sub-50-nm HEMT system.

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50-nm self-aligned-gate pseudomorphic AlInAs/GaInAs high electron mobility transistors

Cited by 397 publications

References 21 publications

Fabrication of GaAs MISFET with nm-thin oxidized layer formed by UV and ozone process

Fabrication of GaAs MISFET with nm-thin oxidized layer formed by UV and ozone process

InAlSb/InAs/AlGaSb Quantum Well Heterostructures for High-Electron-Mobility Transistors

50-nm Self-Aligned and “Standard” T-gate InP pHEMT Comparison: The Influence of Parasitics on Performance at the 50-nm Node

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