Proceedings Electronic Components and Technology, 2005. ECTC '05.
DOI: 10.1109/ectc.2005.1441416
|View full text |Cite
|
Sign up to set email alerts
|

50 Micron Pitch Wafer Level Packaging Testbed with Reworkable IC- Package Nano Interconnects

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
2
0

Publication Types

Select...
4
1

Relationship

0
5

Authors

Journals

citations
Cited by 8 publications
(2 citation statements)
references
References 5 publications
0
2
0
Order By: Relevance
“…14 and SnAg3.OCul .5. The solders, which contain additional impurities of Au and Cu, were lab fabricated.…”
Section: Experiments On Solidification Front Experimental Proceduresmentioning
confidence: 99%
See 1 more Smart Citation
“…14 and SnAg3.OCul .5. The solders, which contain additional impurities of Au and Cu, were lab fabricated.…”
Section: Experiments On Solidification Front Experimental Proceduresmentioning
confidence: 99%
“…As explained in [11,12] it is planed to increase the pitch sizes down to 20 ptm in the next years. FE simulations were already carried out in order to prove the concepts of these interconnections with bump diameters of 50 ptm to 20 ptm [13,14]. In [15] it was already explained that material behaviour changes with size and possible reasons for that are explained in [16].…”
mentioning
confidence: 98%