5.8 A 4.7nW 13.8ppm/°C self-biased wakeup timer using a switched-resistor scheme

Jang, Taekwang; Choi, Myungjoon; Jeong, Seokhyeon; Bang, Suyoung; Sylvester, Dennis; Blaauw, David

doi:10.1109/isscc.2016.7417927

Cited by 38 publications

(19 citation statements)

References 6 publications

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“…A 4-stage differential ring oscillator employing an ultra-low-power leakage-based delay cell is adopted to keep the oscillator power below 60 nW ( Fig. 5) [8]. A subthreshold PTAT current bias is used to lower the DCO temperature drift while exploiting a nW oscillator topology.…”

Section: Timer Architecturementioning

confidence: 99%

“…Alternatively, this paper presents a wakeup timer employing a digital-intensive FLL (DFLL) architecture to fully exploit the advantages of advanced CMOS processes, thus allowing low area, low power and low supply voltage. The proposed timer achieves the best energy efficiency (0.43 pJ/cycle) at the lowest supply voltage (0.7 V) over the state of the art [2], [3], [5], [8]- [11], while maintaining excellent on-par long-term stability (Allan deviation floor below 20 ppm) in a small area (0.07 mm 2 in 40-nm CMOS). These advances are enabled by the use of a bang-bang DFLL architecture employing a chopped dynamic comparator and a low-power high-resolution self-biased Σ∆ digitally-controlled oscillator (DCO).…”

Section: Introductionmentioning

confidence: 99%

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A 0.7-V 0.43-pJ/cycle Wakeup Timer Based on a Bang-Bang Digital-Intensive Frequency-Locked-Loop for IoT Applications

Ding

Zhou

Liu

et al. 2018

IEEE Solid-State Circuits Lett.

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A 40-nm CMOS wakeup timer employing a bangbang digital-intensive frequency-locked loop (DFLL) for Internetof-Things (IoT) applications is presented. A self-biased Σ∆ Digitally Controlled Oscillator (DCO) is locked to an RC time constant via a single-bit chopped comparator and a digital loop filter. Such highly digitized architecture fully exploits the advantages of advanced CMOS processes, thus enabling operation down to 0.7 V and a small area (0.07 mm 2 ). Most circuitry operates at 32× lower frequency than the DCO in order to reduce the total power consumption down to 181 nW. High frequency accuracy and a 10× enhancement of long-term stability is achieved by the adoption of chopping to reduce the effect of comparator offset and 1/f noise and by the use of Σ∆ modulation to improve the DCO resolution. The proposed timer achieves the best energy efficiency (0.43 pJ/cycle at 417 kHz) over prior art while keeping excellent on-par long-term stability (Allan deviation floor <20 ppm) and temperature stability (106 ppm/ o C).

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Section: Timer Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 0.7-V 0.43-pJ/cycle Wakeup Timer Based on a Bang-Bang Digital-Intensive Frequency-Locked-Loop for IoT Applications

Ding

Zhou

Liu

et al. 2018

IEEE Solid-State Circuits Lett.

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“…This approach ensures that there are no delay elements contributing to the oscillation period, thus achieving an excellent temperature coefficient while maintaining ultra-low power consumption. The work in [10] demonstrated power consumption of 4.7 nW while maintaining a frequency inaccuracy of less than 20 ppm/°C.…”

Section: Wake-up Timermentioning

confidence: 99%

Millimeter-scale computing platform for next generation of Internet of Things

Jang

Choi

Shi

et al. 2016

2016 IEEE International Conference on RFID (RFID)

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The internet of things has enabled the communication of "smart" physical objects and improved the quality of machine service to humans. These achievements are based on the synergy of processing information collected by different sources. This trend will continue with the next class of computing platforms enabled by millimeter-scale sensors, diversifying the signal sources including biomedical, climate and surveillance targets. The key challenge of such systems is to achieve small die size, ultra-low power consumption, sufficient communication distance with the limited antenna size and accurate system duty-cycling.

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“…RC oscillators dissipate much less power, but only achieve moderate accuracy, typically more than 2000 ppm over the industrial temperature range [8]- [13], due to the large temperature coefficients (TCs) of integrated resistors.…”

Section: Introductionmentioning

confidence: 99%

A CMOS Dual-<italic>RC</italic> Frequency Reference With ±200-ppm Inaccuracy From −45 °C to 85 °C

Gürleyük

Pedala

Pan

et al. 2018

IEEE J. Solid-State Circuits

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This paper presents a 7-MHz CMOS RC frequency reference. It consists of a frequency-locked loop in which the output frequency of a digitally controlled oscillator (DCO) is locked to the combined phase shifts of two independent RC (Wien bridge) filters, each employing resistors with complementary temperature coefficients. The filters are driven by the DCO's output frequency and the resulting phase shifts are digitized by high-resolution phase-to-digital converters. Their outputs are then combined in the digital domain to realize a temperature-independent frequency error signal. This digitally assisted temperature compensation scheme achieves an inaccuracy of ±200 ppm from −45°C to 85°C after a two-point trim. The frequency reference draws 430 µA from a 1.8-V supply, while achieving a supply sensitivity of 0.18%/V and a 330-ppb Allan deviation floor in 3 s of measurement time. Index Terms-CMOS, digital frequency-locked loop (FLL), digitally controlled oscillator (DCO), integrated frequency reference, RC-based. , where he is currently pursuing the Ph.D. degree, with a focus on the design of energy-efficient CMOS temperature sensors. Fabio Sebastiano (S'09-M'10-SM'17) received the B.Sc. and M.Sc. degrees(cum laude) in electrical engineering from the University of Pisa, Pisa, Italy, in 2003 and 2005, respectively, the M.Sc. degree (cum laude) from the Sant'Anna School of Advanced Studies, Pisa, Italy, in 2006, and the Ph.D. degree from the

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5.8 A 4.7nW 13.8ppm/°C self-biased wakeup timer using a switched-resistor scheme

Cited by 38 publications

References 6 publications

A 0.7-V 0.43-pJ/cycle Wakeup Timer Based on a Bang-Bang Digital-Intensive Frequency-Locked-Loop for IoT Applications

A 0.7-V 0.43-pJ/cycle Wakeup Timer Based on a Bang-Bang Digital-Intensive Frequency-Locked-Loop for IoT Applications

Millimeter-scale computing platform for next generation of Internet of Things

A CMOS Dual-<italic>RC</italic> Frequency Reference With ±200-ppm Inaccuracy From −45 °C to 85 °C

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