A 0.7-V 0.43-pJ/cycle Wakeup Timer Based on a Bang-Bang Digital-Intensive Frequency-Locked-Loop for IoT Applications

Ding, Ming; Zhou, Zhihao; Liu, Yao‐Hong; Traferro, Stefano; Bachmann, Christian; Philips, Kathleen; Foti, Sebastiano

doi:10.1109/lssc.2018.2810602

Cited by 14 publications

(8 citation statements)

References 11 publications

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“…Due to their low-cost integration and high energy efficiency, several RC frequency references have been proposed [7]- [16]. However, the temperature coefficient (TC) of on-chip resistors is typically quite large (>100 ppm/ • C), and thus, the inaccuracy of on-chip RC time constant is typically limited to a few percent over temperature.…”

Section: Green Open Access Added To Tu Delft Institutional Repositorymentioning

confidence: 99%

A 0.9-V 28-MHz Highly Digital CMOS Dual-RC Frequency Reference With ±200 ppm Inaccuracy From −40 °C to 85 °C

Choi¹,

Angevare

Park

et al. 2022

IEEE J. Solid-State Circuits

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This article presents an energy-efficient dual-RC frequency reference intended for wireless sensor nodes. It consists of a digital frequency-locked loop (FLL) in which the frequency of a digitally controlled oscillator (DCO) is locked to a temperature-independent phase shift derived from two different RC poly-phase filters (PPFs). Phase shifts with complementary temperature coefficients (TCs) are generated by using PPFs made from different resistor types (p-poly and silicided p-poly). The phase shift of each filter is determined by a zero-crossing (ZC) detector and then digitized by a digital phase-domain modulator (-M). The results are then combined in the digital domain via fixed polynomials to produce a temperature-independent phase shift. This highly digital architecture enables the use of a sub-1-V supply voltage and enhances energy and area efficiency. The 28-MHz frequency reference occupies 0.06 mm 2 in a 65-nm CMOS process. It achieves a period jitter of 7 ps (1σ ) and draws 142 μW from a 0.9-V supply, which corresponds to an energy consumption of 5 pJ/cycle. Furthermore, it achieves ±200 ppm inaccuracy from −40 • C to 85 • C after a two-point trim.

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Section: Green Open Access Added To Tu Delft Institutional Repositorymentioning

confidence: 99%

A 0.9-V 28-MHz Highly Digital CMOS Dual-RC Frequency Reference With ±200 ppm Inaccuracy From −40 °C to 85 °C

Choi¹,

Angevare

Park

et al. 2022

IEEE J. Solid-State Circuits

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“…Following the FLL architecture, Ding et al [53] proposed a digital-intensive FLL that exploits the advantage of advance CMOS technology nodes. It allows the implementation of a low area, low power, and low supply voltage timer (Fig.…”

Section: ) Power Reduction Techniquesmentioning

confidence: 99%

“…The resistor of FD is implemented with a series combination of non-silicided ppoly and n-poly resistors with opposite temperature coefficients (TC). Such implementation provides first-order compensation in temperature variation [53]. A dynamic comparator compares the output of the FD, which is then fed to a digital filter and locks the frequency of the digitallycontrolled oscillator.…”

Section: ) Power Reduction Techniquesmentioning

confidence: 99%

Fully-Integrated Timers for Ultra-Low-Power Internet-of-Things Nodes—Fundamentals and Design Techniques

et al. 2022

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Driven by the momentum toward compact and low-power Internet-of-Things (IoT) systems, the research on fully-integrated and energy-efficient kHz-to-MHz timers increased explosively. This article examines recent publications on timers and classifies them into two major categories: open-loop-based and close-loop-based timers. Upon introducing the basic parameters for characterizing a timer, we perform an extensive investigation to gain insights into recent state-of-the-art works. We also discuss in detail the comparison between the two classes of timers. With the aid of the state-of-the-art, we present a comprehensive review from multiple perspectives, such as Energy Efficiency, Temperature Coefficient, Temperature Range, Figure-of-Merit, etc.

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“…Ming Ding et al presented a wakeup timer for the (IoT applications [31]. ADPLL consists of a bangbang DFLL architecture and a self-biased DCO.…”

Section: Adpll For Iot and Ble Applicationsmentioning

confidence: 99%

An analysis of ADPLL applications in various fields

Rai¹,

Marimuthu²

2020

IJEECS

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<span>ADPLL is now an essential component in applications like wireless sensor networks, Internet of things, health care applications, agricultural applications, etc, and also due the requirement of digital implementation by the industries. ADPLL consists of a phase detector, loop filter and digital controlled oscillator. The conventional PLL and digital PLL used for frequency synthesis, clock recovery circuit and synchronization give imprecise performance with respect to reliability, speed, power consumption, noise, locking speed, cost, etc. ADPLL overcomes the drawbacks of conventional PLL and digital PLL. In this paper, different approaches followed in All Digital Phase Locked Loop (ADPLL) for various applications are reviewed and their performance is compared based on components, modulation functions, frequency range, power utilization etc. In addition, an ADPLL with wide tuning range and frequency resolution is designed and implemented using automatic placement and routing, time to digital converter, digital loop filter and ring based oscillator. The ADPLL outputs and the results are analyzed with micro wind tool. The design gives a frequency range from 1.0-5.5GHz with low power consumption and it can also be used for Clock generation applications. </span>

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A 0.7-V 0.43-pJ/cycle Wakeup Timer Based on a Bang-Bang Digital-Intensive Frequency-Locked-Loop for IoT Applications

Cited by 14 publications

References 11 publications

A 0.9-V 28-MHz Highly Digital CMOS Dual-RC Frequency Reference With ±200 ppm Inaccuracy From −40 °C to 85 °C

A 0.9-V 28-MHz Highly Digital CMOS Dual-RC Frequency Reference With ±200 ppm Inaccuracy From −40 °C to 85 °C

Fully-Integrated Timers for Ultra-Low-Power Internet-of-Things Nodes—Fundamentals and Design Techniques

An analysis of ADPLL applications in various fields

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