48-Mode Reconfigurable Design of SDF FFT Hardware Architecture Using Radix-3<sup>2</sup> and Radix-2<sup>3</sup> Design Approaches

Shih, Xin-Yu; Liu, Yue-Qu; Chou, Hong-Ru

doi:10.1109/tcsi.2017.2654451

Cited by 23 publications

(4 citation statements)

References 25 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…SDF FFT architectures are the most common pipelined architectures used to process NP2 FFTs [19], [21], [22], [23], [24], [25], [26], [27]. Fig.…”

Section: Sdf Fft Architecturesmentioning

confidence: 99%

“…Nowadays, pipelined FFT hardware architectures for NP2 sizes mostly consider single-path delay feedback (SDF) architectures [18], [19], [20], [21], [22], [23], [24], [25], [26], with the exception of [27]. However, for NP2 sizes, SDF architectures are not as efficient as could be expected: Although SDF architectures process data in series at a rate of one sample per clock cycle, the butterflies that they use operate data in parallel.…”

mentioning

confidence: 99%

See 1 more Smart Citation

Serial Butterflies for Non-Power-of-Two FFT Architectures in 5G and Beyond

Bautista

Garrido

López‐Vallejo

2023

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

This paper presents new serial butterflies for nonpower-of-two (NP2) fast Fourier transform (FFT) architectures. The paper considers radices 2, 3, 4, and 5, which are used in FFTs for 5G systems. Current designs for non-power-of-two FFTs are mostly based on the single-path delay feedback (SDF) architecture. This type of architecture processes data arriving in series. However, it uses butterflies with several parallel inputs. This results in low utilization, as the butterflies have to wait for all the inputs before they start to process them. Conversely, the proposed approach allows to calculate the butterflies on data that arrive in series. This removes waiting times and reduces the number of hardware components such as multipliers and adders. As a result, the proposed butterflies achieve high performance and provide a significant reduction in area and power consumption with respect to parallel butterflies. Thus, they are an efficient solution when data must be processed in series in the butterflies.

show abstract

“…SDF FFT architectures are the most common pipelined architectures used to process NP2 FFTs [19], [21], [22], [23], [24], [25], [26], [27]. Fig.…”

Section: Sdf Fft Architecturesmentioning

confidence: 99%

mentioning

confidence: 99%

Serial Butterflies for Non-Power-of-Two FFT Architectures in 5G and Beyond

Bautista

Garrido

López‐Vallejo

2023

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

show abstract

“…[10] 𝒚 [14] 𝒚 [3] 𝒚 [7] 𝒚 [11] 𝒚 [15] 𝒚[0] 𝒚 [1] 𝒚 [2] 𝒚 [3] 𝒚 [4] 𝒚 [5] 𝒚 [6] 𝒚 [7] 𝒚 [8] 𝒚 [9] 𝒚 [10] 𝒚 [11] 𝒚 [12] 𝒚 [13] 𝒚 [14] 𝒚 [15] factor memories, and control circuitry, thereby achieving the highest efficiency in terms of energy per transform and area per throughput-see the end of Section V for more details.…”

Section: B Smul-fft Architecture Detailsmentioning

confidence: 99%

“…FFT architectures generally fall into four categories [14]: (i) iterative architectures, which require the smallest area but result in the lowest throughput and highest latency, (ii) serial pipelined architectures, which can process one complex sample per clock cycle, (iii) parallel pipelined architectures, which process multiple complex samples per clock cycle, and (iv) fully-unrolled architectures, which achieve the highest throughput by processing a full vector every clock cycle. While the bulk of research on FFT designs focuses on serial and parallel pipelined architectures, see e.g., [15]- [18], fully-unrolled architectures attracted less attention but appear to be the most suitable for beamspace transforms-see Section III-B for a detailed discussion. We note that analog beamspace transforms have been proposed in [19], but recent studies have shown that all-digital architectures using digital transforms can be advantageous in practice [20], [21].…”

mentioning

confidence: 99%

SMUL-FFT: A Streaming Multiplierless Fast Fourier Transform

Mirfarshbafan

Taner

Studer

2021

IEEE Trans. Circuits Syst. II

View full text Add to dashboard Cite

Beamspace processing is an emerging paradigm to reduce hardware complexity in all-digital millimeter-wave (mmWave) massive multiple-input multiple-output (MIMO) basestations. This approach exploits sparsity of mmWave channels but requires spatial discrete Fourier transforms (DFTs) across the antenna array, which must be performed at the baseband sampling rate. To mitigate the resulting DFT hardware implementation bottleneck, we propose a fully-unrolled Streaming MUltiplierLess (SMUL) fast Fourier Transform (FFT) engine that performs one transform per clock cycle. The proposed SMUL-FFT architecture avoids hardware multipliers by restricting the twiddle factors to a sum-of-powers-of-two, resulting in substantial power and area savings. Compared to state-ofthe-art FFTs, our SMUL-FFT ASIC designs in 65 nm CMOS demonstrate more than 45% and 17% improvements in energyefficiency and area-efficiency, respectively, without noticeably increasing the error-rate in mmWave massive MIMO systems. I. INTRODUCTIONMillimeter-wave (mmWave) communication [1], [2] promises significantly increased data-rates due to the availability of large contiguous frequency bands. Massive multiuser multipleinput multiple-output (MU-MIMO) [3] is a key technology to combat the high path loss of mmWave propagation [2] while enabling simultaneous communication with multiple user equipments (UEs) in the same frequency band. The higher baseband sampling rates needed to support larger bandwidths at mmWave frequencies, combined with the large number of antennas in massive MU-MIMO, result in new challenges for analog and digital hardware design. A. Fast Fourier Transforms for Beamspace ProcessingMmWave channels typically comprise only a few dominant propagation paths [1], [2], making them sparse in the beamspace domain [4]- [9]. Beamspace processing exploits this sparsity to reduce the computational complexity of baseband processing [10]-[12]. This approach, which is described in detail in Section II-A, calls for spatial discrete Fourier transforms (DFTs) operated at the baseband sampling rate in order to convert the received signals at the antenna array into the beamspace domain-in high-bandwidth mmWave communication systems, billions of spatial DFTs must be computed per second.

show abstract