45nm High-k/Metal-Gate CMOS Technology for GPU/NPU Applications with Highest PFET Performance

Huang, Huan-Tsung; Liu, Y.C.; Hou, Yunfei; Chen, Renqiang; Lee, C.H.; Chao, Yung-Ching; Hsu, P.F.; Chen, C.L.; Guo, Wei; Wei, Yang; Perng, Tsu-Hsiu; Shen, Jeng-Jung; Yasuda, Y.; Gotō, Kenichi; Chen, C.C.; Huang, Kevin; Chuang, Harry; Diaz, C.H.; Liang, Mong

doi:10.1109/iedm.2007.4418924

Cited by 9 publications

(4 citation statements)

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“…As illustrated in Figure 1, these innovations include channel mobility enhancement by process-induced strain [4][5][6][7][8][9][10], Tinv scaling with gate tunneling reduction by high-K/metal gate [11][12][13], and electrostatic control improvement by transition from planar single gate to 3D FinFET/Multi-Gate FET (MUGFET) structures [14][15][16][17][18][19][20]. These transistor performance enhancements have also increased process complexity significantly.…”

Section: Device Scaling Trend and New Tcad Challengesmentioning

confidence: 99%

Expanding role of predictive TCAD in advanced technology development

Diaz

2013

2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

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Section: Device Scaling Trend and New Tcad Challengesmentioning

confidence: 99%

Expanding role of predictive TCAD in advanced technology development

Diaz

2013

2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

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“…In addition, there are also NPU, DPU, etc. [79][80][81]. FPGA is a processor for developers to customize; usually, an image processor integrates machine vision perception and recognition algorithms.…”

Section: Differences and Similarities Between Human Vision And Bionic...mentioning

confidence: 99%

“…For example, Google has developed an ASIC-based TPU that is dedicated to accelerating the computing power of deep neural networks[78]. In addition, there are also NPU, DPU, etc [79][80][81]…”

mentioning

confidence: 99%

Robot Bionic Vision Technologies: A Review

Zhang¹,

Lee

2022

Applied Sciences

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The visual organ is important for animals to obtain information and understand the outside world; however, robots cannot do so without a visual system. At present, the vision technology of artificial intelligence has achieved automation and relatively simple intelligence; however, bionic vision equipment is not as dexterous and intelligent as the human eye. At present, robots can function as smartly as human beings; however, existing reviews of robot bionic vision are still limited. Robot bionic vision has been explored in view of humans and animals’ visual principles and motion characteristics. In this study, the development history of robot bionic vision equipment and related technologies are discussed, the most representative binocular bionic and multi-eye compound eye bionic vision technologies are selected, and the existing technologies are reviewed; their prospects are discussed from the perspective of visual bionic control. This comprehensive study will serve as the most up-to-date source of information regarding developments in the field of robot bionic vision technology.

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“…Hf-based high-k gate dielectric was used in this work. A key challenge in integrating high-k dielectrics and metal gate into a conventional CMOS flow is to avoid film stack degradation from thermal cycles and at the same time preserve the benefits of the channel mobility enhancing techniques [4].…”

Section: Device Architecture and Process Integrationmentioning

confidence: 99%

32nm gate-first high-k/metal-gate technology for high performance low power applications

Diaz

Gotō

Huang

et al. 2008

2008 IEEE International Electron Devices Meeting

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A 32nm gate-first high-k/metal-gate technology is demonstrated with the strongest performance reported to date to the best of our knowledge. Drive currents of 1340/940 μA/μm (n/p) are achieved at I off =100 nA/μm, V dd =1V, 30nm physical gate length and 130nm gate pitch. This technology also provides a high-Vt solution for high-performance low-power applications with its high drive currents of 1020/700 μA/μm (n/p) at total I off ~1 nA/μm @ V dd = 1V.Low sub-threshold leakage was achieved while successfully containing I boff and I goff well below 1nA/um. Ultra high density 0.15 um 2 SRAM cell is fabricated by high NA 193nm immersion lithography. Functional 2Mb SRAM test-chip in 32nm design rule has been demonstrated with a controllable manufacturing window.

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45nm High-k/Metal-Gate CMOS Technology for GPU/NPU Applications with Highest PFET Performance

Cited by 9 publications

References 0 publications

Expanding role of predictive TCAD in advanced technology development

Expanding role of predictive TCAD in advanced technology development

Robot Bionic Vision Technologies: A Review

32nm gate-first high-k/metal-gate technology for high performance low power applications

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