45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications

Iyer, Subramanian S.; Freeman, G.; Brodsky, Colin J.; Chou, A.; Corliss, Dan; Jain, S.; Lustig, N.; McGahay, V.; Narasimha, S.; Norum, J.; Nummy, Karen; Parries, P.; Sankaran, S.; Sheraw, C.; Varanasi, Pushkara Rao; Wang, G.; Weybright, M.; Yu, Xiaojun; Crabbé, E.F.; Agnello, P.

doi:10.1147/jrd.2011.2108112

Cited by 17 publications

(6 citation statements)

References 24 publications

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“…It is important to note that certain acoustic properties of the FEOL stack were unknown or could not be shared by the foundry. Several processing parameters, including STI fill, silicide, stress liners, and metal contacts to Si [8] contribute substantially to the effective acoustic velocity and stress distribution in the resonator and surrounding ABRs. The resonator is designed to operate in a 1D longitudinal mode at 12 GHz assuming Si and SiO 2 in and around the resonant cavity.…”

Section: Resultsmentioning

confidence: 99%

Si-based unreleased hybrid MEMS-CMOS resonators in 32nm technology

Marathe

Wang

Weinstein

2012

2012 IEEE 25th International Conference on Micro Electro Mechanical Systems (MEMS)

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This work presents the first unreleased Silicon resonators fabricated at the transistor level of a standard CMOS process, and realized without any release steps or packaging. These unreleased bulk acoustic resonators are driven capacitively using the thin gate dielectric of the CMOS process, and actively sensed with a Field Effect Transistor (FET) incorporated into the resonant body. FET sensing using the high , high performance transistors in CMOS amplifies the mechanical signal before the presence of parasitics. This enables RF-MEMS resonators at orders of magnitude higher frequencies than possible with passive devices. First generation CMOS-MEMS Si resonators with Acoustic Bragg Reflectors are demonstrated at 11.1 GHz with ~17 and a total footprint of 5µm × 3µm using IBM's 32nm SOI technology.

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Section: Resultsmentioning

confidence: 99%

Si-based unreleased hybrid MEMS-CMOS resonators in 32nm technology

Marathe

Wang

Weinstein

2012

2012 IEEE 25th International Conference on Micro Electro Mechanical Systems (MEMS)

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“…Similarly, the dimensions and location and processing method of the silicide contacts to the PolySi gate and the source/ drain regions affect the aspect ratio and the mode shape in the thickness dimension resulting in spurious modes. Copper contacts made to the source/drain regions may produce "anchoring points" or different boundary conditions from those offered by the low-k dielectric (SiCOH) surrounding the resonant cavity [16]. Several of these parameters and properties of the FEOL stack were unknown or could not be shared by the foundry resulting in compromised device performance in first-generation devices.…”

Section: Discussion Of Performancementioning

confidence: 99%

“…1). Structurally, the drive capacitor consists of PolySi gate material and a p-doped or n-doped SCS device layer acting as capacitor plates with the SiON gate dielectric between them [16]. On the sense side, a foundry-provided nFET is modified to incorporate it within the resonant cavity along with the drive capacitor on the same device layer.…”

Section: Rbts In Ibm's 32soi Technologymentioning

confidence: 99%

Resonant body transistors in standard CMOS technology

Marathe

Wang

Mahmood

et al. 2012

2012 IEEE International Ultrasonics Symposium

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“…eDRAM access device Due to reliability and process commonality considerations, the 22-nm technology eDRAM access device maintained the same electrical gate dielectric thickness as in the 32-nm technology node. Active-area (i.e., patterned SOI) pitch and particularly active-area space and contacted-gate-pitch scaling offered a path to cell scaling despite the need to maintain the electrical gate length and width for short-channel control and minimization of threshold variation due to random-dopant fluctuation (RDF) [12]. In situ-doped epitaxial Si:C (eSiC) stressor diffusions are used as a performance-enhancement feature for all nFET devices in the 22 nm technology.…”

Section: Pre-doped Substrate and Deep Trenchmentioning

confidence: 99%

Performance-optimized gate-first 22-nm SOI technology with embedded DRAM

et al. 2015

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IBM's high-performance 22-nm silicon-on-insulator (SOI) technology is the enabling physical foundation of IBM POWER8i processors. This paper describes, for the first time in detail, some of the unique aspects of the silicon processing, the features that enabled the industry-leading chip-level performance, and some aspects of the collaborative approach between technology and design teams that enabled both first-time-right silicon and rapid yield improvement. Most critical to the processor functional capability and power-performance achievements are the high-density on-chip memory in the form of embedded DRAM and the high-performance FET device designs based on a low-parasitic-capacitance gate-first FET architecture. Extensive on-chip analog functions are enabled by an additional comprehensive set of devices available in the technology. Fifteen levels of metal with five metal levels at an 80-nm pitch provide the interconnect and power distribution. We describe the pattern resolution enhancement strategy as well as motivation and structural aspects of the innovative features, from the low-resistance N+ epitaxy substrate under the SOI to a dual-embedded source-drain architecture and a highly scaled gate dielectric.

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45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications

Cited by 17 publications

References 24 publications

Si-based unreleased hybrid MEMS-CMOS resonators in 32nm technology

Si-based unreleased hybrid MEMS-CMOS resonators in 32nm technology

Resonant body transistors in standard CMOS technology

Performance-optimized gate-first 22-nm SOI technology with embedded DRAM

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