44.3: 513‐ppi Liquid Crystal Display Using C‐Axis Aligned Crystalline Oxide Semiconductor with Narrow Bezel and Aperture Ratio Greater Than 50%

Toyotaka, Kouhei; Kaneyasu, Makoto; Yamashita, Akio; Jikumaru, Mika; Koyama, Jun; Yamazaki, Shunpei; Hayakawa, Masahiko; Katayama, Masahiro; Kanzaki, Yohsuke; Matsukizono, Hiroshi; Kaneko, Seiji; Mori, Shigeyasu; Matsuo, Takami; Oda, Akihiro

doi:10.1002/j.2168-0159.2014.tb00166.x

Cited by 7 publications

(7 citation statements)

References 10 publications

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“…Concerning main driving signals, instead of using 50%-duty-ratio clock signals, using 25%-duty-ratio clock signals made power consumption of a gate driver circuit lowered by 57.3% [6] and ΔV TH in an a-Si:H TFT reduced by 62.5% [8]. Thus, low-dutyratio clock signals as main driving signals have been applied to practical displays [11]. Although using more clock signals can lead to lower duty ratios, the required layout area will correspondingly increase, which would be disadvantageous to narrow-bezel applications.…”

Section: Low-power Approachesmentioning

confidence: 99%

“…Integrating gate driver circuits on glass substrates has been extensively investigated for active-matrix liquid crystal displays (AMLCDs) and active-matrix organic light-emitting diode (AMOLED) displays because it can make panels more compact, and mechanically reliable, and reduce the fabrication cost by eliminating external integrated circuits (ICs) and related processes [1]- [11]. Fig.…”

Section: Introductionmentioning

confidence: 99%

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7‐1: Invited Paper: Application of Low‐Frequency Clock Signals to Gate Driver Circuits

Lin

Cheng

2017

Symp Digest of Tech Papers

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Section: Low-power Approachesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

7‐1: Invited Paper: Application of Low‐Frequency Clock Signals to Gate Driver Circuits

Lin

Cheng

2017

Symp Digest of Tech Papers

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“…Here, we discuss the circuit configurations of a scan driver [20] and data circuit that can be used to realize a narrow bezel.…”

Section: Circuitmentioning

confidence: 99%

69-3: 806-ppi 4K2K LC Display using Top-gate Self-aligned CAAC-OS FET

Shishido

Takahashi

Toyotaka

et al. 2016

SID Symposium Digest of Technical Papers

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We developed a high-mobility oxide semiconductor material and made a 5.46ƍƍ prototype of 806-ppi 4K2K liquid crystal display using CAAC-OS FET that has a top-gate structure. The top-gate structure caused the parasitic capacitance to be small, resulting in a bezel width of 0.675 mm. Author Keywordscrystalline OS, LCD, narrow bezel, high mobility, ultra-high resolution, top-gate self-aligned (TGSA) type BackgroundRecently the demand for high-resolution narrow-bezel panels has increased due to their use in small and intermediate-sized displays such as smartphones. Low-temperature polysilicon (LTPS) is often used for the backplanes of such displays. LTPS transistors possess high mobilities and low driving voltages. However, LTPS has several disadvantages including high power consumption when displaying still images due to high leakage current (I off ), high cost, multiple processes, and the use of special equipment such as laser crystallization apparatus that use linear laser beams, and ion-doping apparatus. The I off of LTPS transistors are larger than those of amorphous silicon (a-Si) and oxide semiconductor (OS) transistors. Therefore, it is necessary to reduce the resistance or reduce I off by splitting the voltage between the drain and the source. Furthermore, because the grain boundary may induce high I off , the transistors must be made in series to reduce the possibility of dot defects. Therefore, double-gate structures are adopted for the pixel circuits of displays. Consequently, the aperture ratio is small at higher resolutions.Currently, a-Si is used as the backplane for large displays such as TVs. To achieve the resolution required for ultra-high definition (4 or 8K) and a driving frequency of 120 Hz, a replacement material for a-Si must be identified; one candidate replacement material is OS. Transparent amorphous oxide semiconductors were proposed by Kamiya, Hosono, et al., who claimed that amorphous structures are ideal [6-8], whereas we have developed crystalline IGZO.We reported c-axis-aligned crystalline IGZO (CAAC-IGZO) and nanocrystalline IGZO (nc-IGZO), which have crystal morphologies different from those of single-crystal and amorphous IGZO [9][10][11][12]. Researchers at Cornell University have also investigated CAAC-OS [13][14][15][16][17][18]. In CAAC-IGZO films, atomic arrangement parallel to the substrate surface was observed using cross-sectional transmission electron microscopy (TEM). X-ray diffraction analysis revealed a peak at approximately 31q, indicating c-axis alignment, whereas a-b plane alignment was not observed. Furthermore, no clear grain boundary was observed by plane-view TEM. CAAC-IGZO FETs have extremely low I off values on the order of yoctoamperes per micrometer (10 24 A/Pm) owing to their low carrier densities. These FETs are less likely to suffer from shortchannel effects and are thus suitable for scaling [19]. Consequently, OS is expected to be useful for next-generation high-resolution displays.OS is generally considered unsuitable for high-resolution, small d...

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“…In recent years, displays of portable devices have increasingly exhibited high resolution and narrow bezel to improve the visual experience of users [4], [5]. However, as the resolution of AMLCDs increases, the pixels become smaller, so the pitch of the gate driver circuit must be decreased [6], [7]. Also, to satisfy the requirement of a narrow bezel, the width of the layout for the gate driver circuit should be small.…”

Section: Introductionmentioning

confidence: 99%

Simplified Gate Driver Circuit for High-Resolution and Narrow-Bezel Thin-Film Transistor Liquid Crystal Display Applications

Lin

Chen

Ciou

et al. 2015

IEEE Electron Device Lett.

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A novel gate driver circuit composed of four thin-film transistors (TFTs) and two capacitors is developed. Three-phase overlapping clock signals are used in multi-function input TFT and driving TFT, so the proposed circuit can have a simple structure. The electrical characteristics of a fabricated amorphous-indium-gallium-zinc-oxide (a-IGZO) TFT are measured to establish the model of HSPICE simulation. Simulated results confirm that the proposed gate driver circuit generates stable gate pulses according to the specification of a 5.46" FHD panel and the single-stage layout area is 400 μm × 126 μm. These specifications are favorable for high-resolution and narrow-bezel active-matrix liquid crystal displays (AMLCDs).Index Terms-Gate driver circuit, high-resolution, narrow-bezel, thin-film transistor (TFT).C.-L. Lin is with the

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44.3: 513‐ppi Liquid Crystal Display Using C‐Axis Aligned Crystalline Oxide Semiconductor with Narrow Bezel and Aperture Ratio Greater Than 50%

Abstract: An ultra-high resolution 513-ppi liquid crystal display with a narrow 1-mm bezel and an aperture ratio greater than 50 was fabricated. A highly reliable channel-etched c-axis aligned crystalline oxide semiconductor (CAAC-OS) was used in a backplane.

Cited by 7 publications

References 10 publications

7‐1: Invited Paper: Application of Low‐Frequency Clock Signals to Gate Driver Circuits

7‐1: Invited Paper: Application of Low‐Frequency Clock Signals to Gate Driver Circuits

69-3: 806-ppi 4K2K LC Display using Top-gate Self-aligned CAAC-OS FET

Simplified Gate Driver Circuit for High-Resolution and Narrow-Bezel Thin-Film Transistor Liquid Crystal Display Applications

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