42‐3: Invited Paper: A 4Gbps/lane Column Driver for 8K UHD 120Hz Display Larger than 85‐inches

Abstract

A 4Gbps/lane column driver is implemented in 1.8V 0.13-μm high-voltage CMOS process for 8K UHD 120Hz displays. The proposed column driver presents auto-calibrated 4Gbps receiver per lane to cover up to 8K UHD 120Hz 10bit display with two lanes and can drive 8K UHD panel larger than 85-inches. Measured results show that a 4Gbps/lane column driver with auto equalizer calibration technique to adaptively compensate wide variation of channel length, power supply and temperature simultaneously.

A clock embedded intra‐panel interface with 1.96% data overhead for beyond 8K displays

“…In order to compare the data transmission time between 9b/10b channel coding method 6 and the ACC method, a signal indicating the data decoding area in the display driver IC was measured. Data encoding and decoding operate in the pixel data area, and the time required for pixel data transmission can be compared according to each data coding method.…”

“…The challenge for meeting the high data rate between the timing controller and the display driver IC is high channel losses introduced by the large display panel sizes. To overcome this challenge, it is necessary to minimize protocol overhead to guarantee the efficient data transmission 6 ; also, accurate in situ eye margin measurement method is required for optimized eye margin. 7 In this paper, we propose a 6Gb/s intra-panel interface receiver in 0.18-μm process with advanced channel coding (ACC) and on-chip eye margin tester (EMT).…”

23‐3: Distinguished Paper: A Clock Embedded Intra‐panel Interface with 1.96% Data Overhead for Beyond 8K Displays

“…The challenge for meeting the high data rate between the timing controller and the display driver IC is high channel losses introduced by the large display panel sizes. To overcome this challenge, it is necessary to minimize protocol overhead to guarantee the efficient data transmission [1], also accurate in-situ eye margin measurement method is required for optimized eye margin [2].…”

P‐60: An 8Gbps Receiver for 8K Large‐Size Display

“…2-pair or even 4-pair receivers per source driver are required due to the increasing data rate, and it causes expensive and difficult system design for panel makers. Therefore, high-speed interfaces supporting more than 4Gbps are published in recent years [1][2][3]. An 8Gbps receiver is proposed to reduce the number of lanes of intra-panel interface to relax the routing difficulty and lower the manufacturing cost for making an 8K large-size display.…”

“…To adapt to different lengths and configurations of channels, CTLE, VGA, DFE are designed to be configurable. Some automatic calibration techniques [3][4] including offset calibration, CTLE boosting gain adaption, VGA gain control and DFE coefficient optimization can be applied to cover the process, supply voltage, temperature (PVT) variations of chip and also tolerate the variations of channel characteristic and the receiver input swing.…”