4.7 A O.4V-V_DD 2.25-to-2.75GHz ULV-SS-PLL Achieving 236.6fs_rms Jitter, −253.8dB Jitter-Power FoM, and −76.1dBc Reference Spur

CMOS phase-locked loops in ISSCC 2023

“…Besides the PLL with low-f REF , reference frequency multiplication technique is also demonstrated in an over-100-GHz PLL [6] with an ultra-low jitter of sub-50 fs rms , in which an ultrawide loop bandwidth of ~50 MHz can be achieved to sufficiently suppress the output jitter of the VCO.…”