4.3 A Multiphase Interpolating Digital Power Amplifier for TX Beamforming in 65nm CMOS

A novel architecture of a digital modulated polar phased-array transmitter with phase modulation (PM) phase-shifting and feed-forward controlled dynamic matching (FFCDM) is presented in this article. Phase-shifting in a PM signal path is utilized in each element, which shares many components including a phase modulator, baseband, and IF components. The characteristics of the proposed architecture are analyzed. With a constant envelope of PM signals, the implicit nonlinearity of the phase shifter in this architecture has low impact on the linearity performance of a phased-array system. Meanwhile, low phase error can be achieved by high-resolution phase interpolation with the digital predistortion (DPD) technique. Efficiency for both saturated and 6-dB back-off power is enhanced by digital power amplifier (DPA) with FFCDM. As a proof of concept, a 3-7 GHz 4-element phased-array transmitter is designed and fabricated in 40-nm CMOS based on the proposed method. The measured root-mean-square (rms) phase error of 0.3 • , effective phase shifting resolution of 9-bit, and peak system efficiency of 38.2% are achieved. For 40 MHz 64-QAM modulation signal, it exhibits EVM of 5.38% and 5.37%, P out of 14.30 and 14.46 dBm, and PAPR of 7.08 and 6.97 at 3.5 and 5.2 GHz, respectively. The measured peak EIRP is 35.6 dBm with a unit antenna gain of 2.98 dBi at 5 GHz. The radiation patterns with 0 • , 15 • , 30 • , and 45 • steering are measured based on monopole antennas. Meanwhile, the array achieves <4.7% and <5.9% EVM for 64-QAM signals with bandwidths of 20 and 40 MHz, respectively.

Section: B Array Characterizationsmentioning

confidence: 94%

A 4-Element Digital Modulated Polar Phased-Array Transmitter With Phase Modulation Phase-Shifting

Qian

Zhou

Yang

et al. 2021

“…As demonstrated in Fig. 15, it is implemented as four NAND-gate-based multiplexers with its input selection control signals of Sign I = I BB,up [11] and Sign Q = Q BB,up [11] [see Fig. 12(a)].…”

Section: B Delay Alignment and The Phase (Sign-bit) Selector 1) Delay Alignmentmentioning

confidence: 99%

A Wideband Four-Way Doherty Bits-In RF-Out CMOS Transmitter

Beikmirza

Shen

Vreede

et al. 2021

We present a wideband, 12-bit four-way Doherty Cartesian digital transmitter (DTX) featuring an innovative 50%-LO signed I/ Q interleaved up-conversion technique that enables close to perfect orthogonal I/ Q summation. The DTX incorporates a compact four-way lumped-element Doherty power combining network to enhance its average efficiency at deep power back-off (DPBO). It comprises a signed second-order hold (SOH) interpolation filter to suppress the sampling spectral replicas significantly. The proposed DTX is realized in a 40-nm bulk CMOS and delivers a peak output power of 27.54 dBm with drain and system efficiencies of 46.35% and 30.77%, respectively, at 5.3 GHz. At 12 dB DPBO, the realized DTX demonstrates a drain efficiency (DE) of 41.74%-39.27% in a 5.2-5.5 GHz band, respectively. Its intrinsic I/ Q image, LO leakage, and C-IMD3/H 3BB for a 200 MHz tone spacing over a 4.8-6.2 GHz band are −64, −65, and −69 dBc, respectively, without calibration. Applying a simple memoryless 2 × 1-D digital pre-distortion, its error vector magnitude and adjacent channel leakage ratio are lower than −31 dB and −39 dBc, respectively, for a six-carrier "40 MHz 256-QAM OFDM" signal with 18 dBm average output power and a 41% average DE. The signed SOH functionality is verified employing a four-carrier "80 MHz 512-QAM OFDM" signal with spectral purity of better than −35 dBc, while its baseband sampling frequency is 675 MHz.

“…In addition, a power-combining network was required to obtain high output power, and the power supply was increased, resulting in potential reliability issues. In contrast, voltage-mode structures [e.g., switchedcapacitor PA (SCPA)] [2], [5], [8], [9] show better reliability (due to fixed voltage swings on all devices) and linearity without using DPD. In fact, the SCPA can exhibit improved linearity compared to analog PAs [10] without compressive behavior when bondwires are properly accounted for.…”

Section: Introductionmentioning

confidence: 99%

A mm-Wave Switched-Capacitor RFDAC

Nguyen

Walling

Zhu

et al. 2022

Self Cite

This article proposes an interleaving switchedcapacitor RF digital-to-analog converter (RFDAC) using an edge combiner within the output stage to implicitly triple its effective clock carrier frequency and enable the mm-wave (mmW) operation. Tripling in the output stage allows for increased energy efficiency, which is further improved by employing an edgecombining-based frequency-tripling delay-locked loop (DLL) in the clock generation network. The clock tripling is performed in each slice of the switched-capacitor PA (SCPA), which allows yet another 3× frequency reduction for the global clock distribution. Finally, a new layout structure accounts for transmission-line (TL) effects, due to the large physical size of the passive capacitor array. Implemented in 22-nm FD-SOI, the prototype achieves P out > 21 dBm, drain efficiency >36%, and system efficiency >22% while operating in the Ka-band at 28 GHz. Modulation at 2.4 Gb/s results in 3.3% EVM and 30.8-dBc adjacent channel leakage ratio (ACLR).