A Wideband Four-Way Doherty Bits-In RF-Out CMOS Transmitter

Abstract

We present a wideband, 12-bit four-way Doherty Cartesian digital transmitter (DTX) featuring an innovative 50%-LO signed I/ Q interleaved up-conversion technique that enables close to perfect orthogonal I/ Q summation. The DTX incorporates a compact four-way lumped-element Doherty power combining network to enhance its average efficiency at deep power back-off (DPBO). It comprises a signed second-order hold (SOH) interpolation filter to suppress the sampling spectral replicas significantly. The proposed DTX is realized in a 40-nm bulk CMOS and delivers a peak output power of 27.54 dBm with drain and system efficiencies of 46.35% and 30.77%, respectively, at 5.3 GHz. At 12 dB DPBO, the realized DTX demonstrates a drain efficiency (DE) of 41.74%-39.27% in a 5.2-5.5 GHz band, respectively. Its intrinsic I/ Q image, LO leakage, and C-IMD3/H 3BB for a 200 MHz tone spacing over a 4.8-6.2 GHz band are −64, −65, and −69 dBc, respectively, without calibration. Applying a simple memoryless 2 × 1-D digital pre-distortion, its error vector magnitude and adjacent channel leakage ratio are lower than −31 dB and −39 dBc, respectively, for a six-carrier "40 MHz 256-QAM OFDM" signal with 18 dBm average output power and a 41% average DE. The signed SOH functionality is verified employing a four-carrier "80 MHz 512-QAM OFDM" signal with spectral purity of better than −35 dBc, while its baseband sampling frequency is 675 MHz.

High-Power Digital Transmitters for Wireless Infrastructure Applications (A Feasibility Study)

“…This bandwidth was mainly restricted by unfortunate resonance in the driver supply bias. However, other (lower power) DTX work [26] shows that large bandwidths (>300 MHz) with good linearity are in reach using a fully digital approach.…”

A Wideband Energy-Efficient Multi-Mode CMOS Digital Transmitter

“…15, the duty cycle generation circuit produces the related eight-phase 12.5%-LO or 25%-LO clocks by bit-wise AND operation of the corresponding LO pairs. It is also worth mentioning that the AND gates are implemented in a symmetrical configuration to equalize the delays of the clocks [33].…”

“…18( Furthermore, each part's LSB units comprise 16 small unit cells (I/Q BB,UP B [15:0]) that occupy a column. Instead of having two separate push-pull banks, every other column of the I/Q RF-DAC matrix is dedicated to the in-phase arrays and their 180 • out-of-phase counterparts [33]. This technique reduces the overall I/Q RF-DAC core size for the same achievable output power, resulting in a highly compact area, smaller parasitics, minimal mismatch, and less power consumption, resulting in improved overall DTX efficiency.…”

A 1-to-4GHz Multi-Mode Digital Transmitter in 40nm CMOS Supporting 200MHz 1024-QAM OFDM signals with more than 23dBm/66% Peak Power/Drain Efficiency

“…have been explored to fully benefit from the high-speed switching and integration capabilities of nanoscale CMOS technologies [1][2][3][4][5]. These DTXs are primarily exploiting a polar or Cartesian architecture.…”

“…Moreover, their phase and amplitude paths must recombine at the output stage without any delay mismatch to maintain linear operation. In contrast, Cartesian DTX variants can handle signals with large modulation bandwidth [3]. Nevertheless, their DE is lower than their polar counterparts owing to the linear combination of orthogonal I/Q vectors, yielding a 3-dB worst-case output power loss at the orthogonal (I/Q) axes.…”