4.1: Low‐Temperature‐Processed IGZO TFTs for Flexible AMOLED with Integrated Gate Driver Circuits

Miura, Kanako; Ueda, T.; Nakano, Satoshi; Saito, Nobuyoshi; Hara, Yukio; Sugi, Keiji; Sakano, Tatsunori; Yamaguchi, Hideyo; Amemiya, Isao; Akimoto, Keiko; Kameoka, Hisashi; Tonotani, Junichi

doi:10.1889/1.3621277

Cited by 22 publications

(19 citation statements)

References 6 publications

(6 reference statements)

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“…3 Some groups have reported comparable stability in TFTs fabricated at low temperature, on plastic, or with alternate materials. [4][5][6][7] However, on the way to achieving this state-of-the-art, we have come across devices with large threshold voltage (V TH ) shift or anomalous behaviors, and understanding the cause of this is of fundamental importance. In this context, we report in this paper the anomalies observed in AOS TFTs under bias stress in the dark, and discuss possible mechanisms.…”

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confidence: 99%

Interpreting anomalies observed in oxide semiconductor TFTs under negative and positive bias stress

et al. 2016

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Oxide semiconductor thin-film transistors can show anomalous behavior under bias stress. Two types of anomalies are discussed in this paper. The first is the shift in threshold voltage (VTH) in a direction opposite to the applied bias stress, and highly dependent on gate dielectric material. We attribute this to charge trapping/detrapping and charge migration within the gate dielectric. We emphasize the fundamental difference between trapping/detrapping events occurring at the semiconductor/dielectric interface and those occurring at gate/dielectric interface, and show that charge migration is essential to explain the first anomaly. We model charge migration in terms of the non-instantaneous polarization density. The second type of anomaly is negative VTH shift under high positive bias stress, with logarithmic evolution in time. This can be argued as electron-donating reactions involving H2O molecules or derived species, with a reaction rate exponentially accelerated by positive gate bias and exponentially decreased by the number of reactions already occurred.

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confidence: 99%

Interpreting anomalies observed in oxide semiconductor TFTs under negative and positive bias stress

et al. 2016

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“…Instability of threshold voltage (Vth) under bias-temperature stress (BTS) is one of the crucial issues concerning practical use. Some groups including our group, previously reported highly stable a-InGaZnO TFTs against BTS on glass substrates [4][5][6] and plastic substrates [7,8].…”

Section: Introductionmentioning

confidence: 99%

70.1L: Late‐News Paper: 10.2‐inch WUXGA Flexible AMOLED Display Driven by Amorphous Oxide TFTs on Plastic Substrate

Saito

Ueda

Miura

et al. 2013

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“…[1,2] Among them, the amorphous Indium-gallium-zinc-oxide (a-IGZO) TFTs, utilizing the a-IGZO thin film as an active channel layer, have stimulated considerable technological interests for scientific research due to their importance in fundamental physics studies and their future potential applications for the next generation of liquid crystal display and organic light-emitting diode. [3,4] However, most inverted staggered structured a-IGZO TFTs have high parasitic capacitance due to the overlap between the gate and source/drain electrodes, known as the gate-todrain overlap capacitance (Cgd).…”

Section: Introductionmentioning

confidence: 99%

46.4: Self‐Aligned Bottom‐Gate Amorphous IGZO Thin Film Transistor using the Back Side Exposure Technique

Park¹,

Lee²,

Choi³

et al. 2013

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In this work, we proposed new fabrication equipment for using the back side exposure technique in Gen.8 glass size and discussed a self-alignment technique for fabrication of a-IGZO TFTs which result in inverted staggered bottom gate devices, to simplify the OLED array processing. The Cgs of a-IGZO TFTs with back side exposure process was lower about 40% than that of a a-IGZO TFTs with typical process. The decrease in capacitance value of the back side exposure process a-IGZO TFTs is because the overlap area between the gate and source/drain electrodes has become decrease. At Vds of 10V, the back side exposure process a-IGZO TFTs represent μsat of 12.43 cm2/Vs, Vth of 0.75V, on-current of 74.4uA, S-Factor of 0.23V/dec.

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4.1: Low‐Temperature‐Processed IGZO TFTs for Flexible AMOLED with Integrated Gate Driver Circuits

Abstract: We have reduced threshold voltage shift of IGZO TFTs processed at 200°C under bias-temperature stress of V g = 20 V at 70°C for 2000 s to 0.22 V by optimizing IGZO deposition and annealing conditions. A flexible AMOLED display with integrated gate driver circuits has been demonstrated.

Cited by 22 publications

References 6 publications

Interpreting anomalies observed in oxide semiconductor TFTs under negative and positive bias stress

Interpreting anomalies observed in oxide semiconductor TFTs under negative and positive bias stress

70.1L: Late‐News Paper: 10.2‐inch WUXGA Flexible AMOLED Display Driven by Amorphous Oxide TFTs on Plastic Substrate

46.4: Self‐Aligned Bottom‐Gate Amorphous IGZO Thin Film Transistor using the Back Side Exposure Technique

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