3D synaptic architecture with ultralow sub-10 fJ energy per spike for neuromorphic computation

Wang, I-Ting; Lin, Yen-Chuan; Wang, Yufen; Hsu, Chia-Yang; Hou, Tuo‐Hung

doi:10.1109/iedm.2014.7047127

Cited by 87 publications

(63 citation statements)

References 11 publications

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“…Fig. 3 The weight update curve for TaO x /TiO 2 resistive synaptic devices [4]. Non-ideal properties include nonlinear weight update, limited on/off ratio, and variations.…”

Section: Resultsmentioning

confidence: 99%

“…Fig. 2 Example of a small scale of crossbar array with TaO x /TiO 2 resistive synaptic devices [4]. The oxygen vacancies migrate between the TaO x and TiO 2 interface under voltage programming pulse thereby modulating the device conductance.…”

Section: Resultsmentioning

confidence: 99%

“…3) a small on/off ratio greatly degrades the learning accuracy ( Fig. 12), thus some of today's devices [4][5][6] become problematic. 4) the algorithm can tolerate the spatial variations but has poor resilience against the temporal variations (Fig.…”

Section: Non-ideal Device Properties and Array Parasiticsmentioning

confidence: 99%

“…We use MNIST handwritten digits dataset [10] for the training, and the recognition accuracy is the metric for the following discussions: 1) to avoid a significant accuracy loss, a 6-bit D (64 multi-levels for resistive synaptic devices) is needed (Fig. 10), which is achievable in today's devices [4][5][6]. 2) the nonlinear weight update slightly decreases the accuracy by a few percentages (Fig.…”

Section: Non-ideal Device Properties and Array Parasiticsmentioning

confidence: 99%

“…Although the synaptic multilevel behavior has been reported in various resistive memories (one example shown in Fig. 2) at device level [4][5][6] and a simple learning algorithm has been experimentally demonstrated at small network level [7], extending the array size to a large-scale is a nontrivial task. In this paper, we discuss the design challenges of scaling up of the array size and present the potential solutions for overcoming these challenges.…”

Section: Introductionmentioning

confidence: 99%

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Scaling-up resistive synaptic arrays for neuro-inspired architecture: Challenges and prospect

Chen

Cao

et al. 2015

2015 IEEE International Electron Devices Meeting (IEDM)

165

116

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The crossbar array architecture with resistive synaptic devices is attractive for on-chip implementation of weighted sum and weight update in the neuro-inspired learning algorithms. This paper discusses the design challenges on scaling up the array size due to non-ideal device properties and array parasitics. Circuit-level mitigation strategies have been proposed to minimize the learning accuracy loss in a large array. This paper also discusses the peripheral circuits design considerations for the neuro-inspired architecture. Finally, a circuit-level macro simulator is developed to explore the design trade-offs and evaluate the overhead of the proposed mitigation strategies as well as project the scaling trend of the neuroinspired architecture.

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“…Fig. 3 The weight update curve for TaO x /TiO 2 resistive synaptic devices [4]. Non-ideal properties include nonlinear weight update, limited on/off ratio, and variations.…”

Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: Non-ideal Device Properties and Array Parasiticsmentioning

confidence: 99%

Section: Non-ideal Device Properties and Array Parasiticsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Scaling-up resistive synaptic arrays for neuro-inspired architecture: Challenges and prospect

Chen

Cao

et al. 2015

2015 IEEE International Electron Devices Meeting (IEDM)

165

116

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Neuromorphic Computing Using Emerging NV Memory Devices

2018

Memories for the Intelligent Internet of Things

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Nonvolatile Memory Materials for Neuromorphic Intelligent Machines

2018

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Recent progress in deep learning extends the capability of artificial intelligence to various practical tasks, making the deep neural network (DNN) an extremely versatile hypothesis. While such DNN is virtually built on contemporary data centers of the von Neumann architecture, physical (in part) DNN of non-von Neumann architecture, also known as neuromorphic computing, can remarkably improve learning and inference efficiency. Particularly, resistance-based nonvolatile random access memory (NVRAM) highlights its handy and efficient application to the multiply-accumulate (MAC) operation in an analog manner. Here, an overview is given of the available types of resistance-based NVRAMs and their technological maturity from the material- and device-points of view. Examples within the strategy are subsequently addressed in comparison with their benchmarks (virtual DNN in deep learning). A spiking neural network (SNN) is another type of neural network that is more biologically plausible than the DNN. The successful incorporation of resistance-based NVRAM in SNN-based neuromorphic computing offers an efficient solution to the MAC operation and spike timing-based learning in nature. This strategy is exemplified from a material perspective. Intelligent machines are categorized according to their architecture and learning type. Also, the functionality and usefulness of NVRAM-based neuromorphic computing are addressed.

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3D synaptic architecture with ultralow sub-10 fJ energy per spike for neuromorphic computation

Cited by 87 publications

References 11 publications

Scaling-up resistive synaptic arrays for neuro-inspired architecture: Challenges and prospect

Scaling-up resistive synaptic arrays for neuro-inspired architecture: Challenges and prospect

Neuromorphic Computing Using Emerging NV Memory Devices

Nonvolatile Memory Materials for Neuromorphic Intelligent Machines

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