3D Memristor Crossbar Architecture for a Multicore Neuromorphic System

Fernando, B. Rasitha; Qi, Yangjie; Yakopcic, Chris; Taha, Tarek M.

doi:10.1109/ijcnn48605.2020.9206929

Cited by 11 publications

(8 citation statements)

References 34 publications

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“…Although the crossbar's latency increases, its design and implementation become significantly simplified. Similar memristor and other non-volatile memory-based neural accelerators have also been studied in prior works (Trivedi and Mukhopadhyay 2014;Manasi and Trivedi 2016;Shafiee et al, 2016;Wang et al, 2016;Mikhailenko et al, 2018;Nasrin et al, 2019;Fernando et al, 2020;Ma et al, 2020;Nasrin et al, 2020;Shukla et al, 2021a). However, our subsequent discussion will highlight how dual-gated control of the memtransistor grid can offer unique co-optimization opportunities not available to current memristor-based crossbar designs.…”

Section: Crossbar Architecture and Timedomain Processingmentioning

confidence: 81%

Higher order neural processing with input-adaptive dynamic weights on MoS2 memtransistor crossbars

Rahimifard

Shylendra²,

Nasrin³

et al. 2022

Front. Electron. Mater

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The increasing complexity of deep learning systems has pushed conventional computing technologies to their limits. While the memristor is one of the prevailing technologies for deep learning acceleration, it is only suited for classical learning layers where only two operands, namely weights and inputs, are processed simultaneously. Meanwhile, to improve the computational efficiency of deep learning for emerging applications, a variety of non-traditional layers requiring concurrent processing of many operands are becoming popular. For example, hypernetworks improve their predictive robustness by simultaneously processing weights and inputs against the application context. Two-electrode memristor grids cannot directly map emerging layers’ higher-order multiplicative neural interactions. Addressing this unmet need, we present crossbar processing using dual-gated memtransistors based on two-dimensional semiconductor MoS2. Unlike the memristor, the resistance states of memtransistors can be persistently programmed and can be actively controlled by multiple gate electrodes. Thus, the discussed memtransistor crossbar enables several advanced inference architectures beyond a conventional passive crossbar. For example, we show that sneak paths can be effectively suppressed in memtransistor crossbars, whereas they limit size scalability in a passive memristor crossbar. Similarly, exploiting gate terminals to suppress crossbar weights dynamically reduces biasing power by ∼20% in memtransistor crossbars for a fully connected layer of AlexNet. On emerging layers such as hypernetworks, collocating multiple operations within the same crossbar cells reduces operating power by ∼15× on the considered network cases.

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Section: Crossbar Architecture and Timedomain Processingmentioning

confidence: 81%

Higher order neural processing with input-adaptive dynamic weights on MoS2 memtransistor crossbars

Rahimifard

Shylendra²,

Nasrin³

et al. 2022

Front. Electron. Mater

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“…Implementation-wise, a system software for neuromorphic hardware must also incorporate hardware constraints, such as constrained neural architecture, limited neuron and synapse capacities, and limited fanin per neuron. We take the architecture of a crossbar [71,72,73,74,75,76,77,78,79], which is commonly used to implement neuromorphic hardware platforms. In a crossbar, bitlines and wordlines are organized in a grid with memory cells connected at their crosspoints to store synaptic weights.…”

Section: System Software Considerations For Neuromorphic Computingmentioning

confidence: 99%

Implementing Spiking Neural Networks on Neuromorphic Architectures: A Review

Huynh¹,

Varshika²,

Paul³

et al. 2022

Preprint

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Recently, both industry and academia have proposed several different neuromorphic systems to execute machine learning applications that are designed using Spiking Neural Networks (SNNs). With the growing complexity on design and technology fronts, programming such systems to admit and execute a machine learning application is becoming increasingly challenging. Additionally, neuromorphic systems are required to guarantee real-time performance, consume lower energy, and provide tolerance to logic and memory failures. Consequently, there is a clear need for system software frameworks that can implement machine learning applications on current and emerging neuromorphic systems, and simultaneously address performance, energy, and reliability. Here, we provide a comprehensive overview of such frameworks proposed for both, platform-based design and hardware-software co-design. We highlight challenges and opportunities that the future holds in the area of system software technology for neuromorphic computing.

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“…Each PE implements neuron and synapse circuitries. A common technique to implement a neuromorphic PE is using an analog crossbar where bitlines and wordlines are organized in a grid with memory cells connected at their crosspoints to store synaptic weights [2,32,40,45,46,51,61,69,100]. Neuron circuitries are implemented along bitlines and wordlines.…”

Section: Introductionmentioning

confidence: 99%

Design-Technology Co-Optimization for NVM-based Neuromorphic Processing Elements

Song¹,

Balaji²,

Das³

et al. 2022

Preprint

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An emerging use-case of machine learning (ML) is to train a model on a high-performance system and deploy the trained model on energy-constrained embedded systems. Neuromorphic hardware platforms, which operate on principles of the biological brain, can significantly lower the energy overhead of a machine learning inference task, making these platforms an attractive solution for embedded ML systems. We present a designtechnology tradeoff analysis to implement such inference tasks on the processing elements (PEs) of a Non-Volatile Memory (NVM)-based neuromorphic hardware. Through detailed circuit-level simulations at scaled process technology nodes, we show the negative impact of technology scaling on the information-processing latency, which impacts the quality-of-service (QoS) of an embedded ML system. At a finer granularity, the latency inside a PE depends on 1) the delay introduced by parasitic components on its current paths, and 2) the varying delay to sense different resistance states of its NVM cells. Based on these two observations, we make the following three contributions. First, on the technology front, we propose an optimization scheme where the NVM resistance state that takes the longest time to sense is set on current paths having the least delay, and vice versa, reducing the average PE latency, which improves the QoS. Second, on the architecture front, we introduce isolation transistors within each PE to partition it into regions that can be individually power-gated, reducing both latency and energy. Finally, on the system-software front, we propose a mechanism to leverage the proposed technological and architectural enhancements when implementing a machine-learning inference task on neuromorphic PEs of the hardware. Evaluations with a recent neuromorphic hardware architecture show that our proposed design-technology co-optimization approach improves both performance and energy efficiency of machine-learning inference tasks without incurring high cost-per-bit. CCS Concepts: • Hardware → Neural systems; Emerging languages and compilers; Emerging tools and methodologies; • Computer systems organization → Data flow architectures; Neural networks.

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3D Memristor Crossbar Architecture for a Multicore Neuromorphic System

Cited by 11 publications

References 34 publications

Higher order neural processing with input-adaptive dynamic weights on MoS2 memtransistor crossbars

Higher order neural processing with input-adaptive dynamic weights on MoS2 memtransistor crossbars

Implementing Spiking Neural Networks on Neuromorphic Architectures: A Review

Design-Technology Co-Optimization for NVM-based Neuromorphic Processing Elements

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