3D interconnects for dense die stack packages

Mirkarimi, Laura; Huynh, Michael; Savalia, P. V.; Oganesian, V.

doi:10.1109/3dic.2009.5306574

Cited by 4 publications

(2 citation statements)

References 2 publications

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“…Many publications over the last several years have indicated that companies are either already manufacturing 3D chips or have plans to do so in the near future [65][66][67][68][69][70][71][72][73][74][75][76][77][78]. Ultimately, the success of any manufacturable 3D integration solution rides on several factors: 1) the choice of TSV technology, which in turn is determined by its compatibility with the rest of the fabrication process, including the bonding stage and method, and the requirements that are placed upon it from a systems perspective; 2) the robustness and thermo-mechanical reliability of the fully integrated structure; and 3) cost/yield considerations.…”

Section: Discussionmentioning

confidence: 99%

3D integration review

Farooq¹,

Iyer²

2011

Sci. China Inf. Sci.

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3-D integration delivers value by increasing the volumetric transistor density with the potential benefit of shorter electrical path lengths through use of the shorter third dimension. Several researchers have studied various aspect of 3Di such as bonding level, through silicon via processes and integration, thermomechanical reliability of the vias, and the impact of the vias on devices. In this paper, we review some of the literature with a view to understanding the key options and challenges in 3Di. We also discuss some important applications of this technology, and the constraints that have to be overcome to make it work.

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Section: Discussionmentioning

confidence: 99%

3D integration review

Farooq¹,

Iyer²

2011

Sci. China Inf. Sci.

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“…Modeling shows therefore that 3Di can deliver benefits that are not possible in the 2D regime. Recent publications (3)(4)(5)(6)(7)(8) are an indication that semiconductor manufacturers agree, and have already started 3D chip production or have plans to do so in the near future. However, 3D fabrication involves critical choices in bonding level and method, and TSV process and integration.…”

Section: Introductionmentioning

confidence: 99%

(Invited) 3D Integration in Silicon Technology

Farooq¹

2011

ECS Trans.

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3Di (3D integration) refers to a family of technologies which enable the stacking of active Si layers with vertical connections between them. 3Di has the ability to enhance chip performance by increasing bandwidth, reducing wire delay, and enabling better power management. Several researchers have investigated TSV (Through Silicon Via) fabrication, insulation, metallization, integration, the impact of TSVs on devices, thermo-mechanical integrity and reliability of TSVs. This paper presents a review of some of these publications in order to understand the options and challenges in 3Di.

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Low cost 3D multilevel interconnect integration for RF and microwave applications

Ghannam

Bourrier

Ourak

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

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This work presents a new and low cost multi-level 3D copper interconnect process for RF and microwave applications. This process extends 3D interconnect integration technologies from silicon to above-IC polymer. Therefore, 3D passive devices and multi-level interconnects can be integrated using a single electroplating step making the process suitable for 3D-MMIC integration. 3D interconnects are realized by patterning the SU-8 to specific locations to create the desired 3D shape. A 3D seed layer is deposited above the SU-8 and the substrate to insure 3D electroplating current flow. The BPN is used as a thick mold for copper electroplating with an aspect ratio as high as 16:1. An optimized electroplating process is later used to grow copper in a 3D technique, insuring transition between all metallic layers. Finally, high-Q (60 @ 6 GHz) power inductors have been designed and integrated above a 50 W RF power LDMOS device, using this process. IntroductionToday, RF and microwave applications demands for increased functionality, higher density integration, better passive device performance, reduced footprint and cost are stressing for new and enhanced integration technologies. To meet these requirements, technologies like 3D-MMIC were introduced [1]- [4]. These technologies look promising because they offer a solution for both miniaturization and passive device performance issues. However, their complexity, cost and processing time increase quickly with each addition of a dielectric or a metallic layer, which hindered their large scale usage. Moreover, the performance of the passive devices is severely limited by the relatively thin dielectric layers. Thus, stacking several dielectric layers is required to improve the performance of these devices which often induces more complications like increased residual stress on the chip and the frequent need for mechanical dielectric leveling steps.In another hand, to overcome 3D-MMIC limitations, a specific 3D interconnect technology is needed to replace current planar technologies used for implementation of passive circuits such as filters, matching networks, transformers ... or for the integration of inductors often realized from bond wires. This implies that the technology must allow the integration of both the interconnect and the vias for underneath connection.Finally, current 3D interconnect technologies are focused on the 3D stacking of integrated circuits, at the IC-fab, or, at package level, to achieve a higher integration density and a smaller footprint of electronic components [5]. Such a technology would be more attractive if it could be applied as well for above-IC passive devices integration. However, this

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3D interconnects for dense die stack packages

Cited by 4 publications

References 2 publications

3D integration review

3D integration review

(Invited) 3D Integration in Silicon Technology

Low cost 3D multilevel interconnect integration for RF and microwave applications

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