3D-interconnect: Visualization of extrusion and voids induced in copper-filled through-silicon vias (TSVs) at various temperatures using X-ray microscopy

Kong, LayWai; Rudack, Andrew C.; Krueger, P. J.; Zschech, Ehrenfried; Arkalgud, Sitaram; Diebold, Alain C.

doi:10.1016/j.mee.2011.04.012

Cited by 38 publications

(15 citation statements)

References 3 publications

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“…The values of the protrusion heights in this study are actually relatively larger than those reported in previous studies. 5,6,9) This is caused by the fact that the via diameter in our study is larger than those in previous studies; previous researchers used smaller vias with diameters less than 10 µm. It is well known that Cu protrusion from TSVs increases with increasing via diameters.…”

Section: Methodsmentioning

confidence: 60%

“…We did not measure the change in the Cu protrusion height at various annealing temperatures because there have already been several reports detailing the measurements of Cu TSV protrusions. 5,6,9) It is clear that the Cu-Ni TSV shows lower via protrusion than the conventional Cu TSV. However, a protrusion height of 1.25 µm is still high enough to cause fracture of the overlying BEOL layer.…”

Section: Methodsmentioning

confidence: 99%

“…3,4) Cu protrusions in TSVs, also known as Cu pumping and Cu extrusion, have been discussed recently in the literature. 5,6) During the fabrication of TSVs, the vias undergo thermal annealing at up to ³450°C with metallization and/or bonding processes at ³250°C. At any high temperature step of the TSV manufacturing process, the copper, which is confined in the via hole, will expand in the vertical direction and subsequently extrude out of the Si wafer surface (due to its higher CTE).…”

Section: Introductionmentioning

confidence: 99%

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Lower Protrusion of a Copper-Nickel Alloy in a Through-Silicon via and Its Numerical Simulation

et al. 2015

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The application of Cu-filled through-silicon via (TSV) in 3-D integrated circuit packaging faces several fabrication and reliability issues. In this study, we introduced a Cu-Ni alloy for TSV filling with a high filling speed and a reduced TSV protrusion. In particular, the characteristics of Cu-Ni via protrusions at various annealing temperatures (³200450°C) were investigated with experimental and numerical analysis and compared with Cu-filled vias. High speed Cu-Ni alloy filling into the vias was achieved without any defects by an electroplating process that used a periodic pulse reverse current waveform. The Cu-Ni alloy TSV showed lower via protrusion than the Cu TSV. The simulated protrusion heights of the Cu-Ni vias were in good agreement with the experimental results. The simulation results also indicated that the Cu-Ni TSVs has smaller protrusions than the Cu TSVs. As the annealing temperature was varied from 200 to 450°C, the protrusions increased gradually and became significant at an annealing temperature of 350°C. When the temperature was increased further, the protrusions became larger due to severe creep deformation. The von Mises stress also increased with increasing annealing temperature, and increased substantially at a temperature of 300°C due to the creep effect. In summary, the Cu-Ni alloy TSVs showed smaller protrusions relative to the Cu TSVs. The stress level of the Cu-Ni via was lower than that of the Cu via. These results indicate that the Cu-Ni alloy TSV had advantages in terms of high speed filling and smaller protrusions, demonstrating its promise as an alternative to current Cu TSV technologies.

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Section: Methodsmentioning

confidence: 60%

Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Lower Protrusion of a Copper-Nickel Alloy in a Through-Silicon via and Its Numerical Simulation

et al. 2015

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“…The high CTE of the filled copper (i.e., 17 × 10 14,15,18 led to copper protrusion on the TSV due to copper atom movement. On the basis of mass balance, several copper cracks and voids (i.e., copper vacancies) remained in the TSV because the copper atoms thermally moved and got out the TSV, [18][19][20][21][22] as confirmed in Fig. 2e.…”

Section: Resultsmentioning

confidence: 72%

“…[14][15][16][17] Copper atoms diffuse from the TSV due to thermal cycling, leading to void formation in the TSV. 18,19 The copper protrusion on the TSV caused respectively by thermal expansion and diffusion of copper lattices and atoms may destroy stacked IC chips. [20][21][22] Copper must be replaced by tungsten 23 or nickel 24,25 to overcome the issue of CTE mismatch.…”

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confidence: 99%

Microvia Filling with Nickel-Tungsten Alloy to Decrease the Coefficient of Thermal Expansion of Electronic Circuit Interconnections

Lin

Huang

Wang

et al. 2015

ECS Electrochemistry Letters

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A nickel-tungsten alloy plating formula was developed to electrochemically fill the microvias of printed circuit boards and the through-silicon vias (TSVs) of wafers. The plating solution was composed of Ni(SO 3 NH 2 ) 2 , citric acid, sodium citrate, Na 2 WO 4 , chloride ions, and 2-mercapto-5-benzimidazolesulfonic acid. A void-free Ni-W superfilling of a microvia and a TSV were achieved. The tungsten content in the filled alloy varied from 1.5 atom% to 5.5 atom%, depending on the plating temperature. The coefficient of thermal expansion of the filled Ni-W was theoretically calculated according the tungsten content, which was lower than that of copper. Microvia filling by copper electroplating has been widely employed to fabricate state-of-the-art printed circuit boards (PCBs) for interconnection, especially for integrated circuit (IC) packaging substrates.1-5 Recently, through-silicon vias (TSVs) have also been metallized by copper electroplating for the interconnection of threedimensional (3D) IC chip stacking packaging. [6][7][8][9][10][11][12][13] Copper is a good conductor but its coefficient of thermal expansion (CTE) is high. Therefore, issues related to CTE mismatch between the conducting materials and the dielectric materials arise in PCB and 3D packaging with high-density interconnections.Numerous authors have reported that the high CTE of the copper filled in the TSVs results in stress impacts on silicon substrates. [14][15][16][17] Copper atoms diffuse from the TSV due to thermal cycling, leading to void formation in the TSV. 18,19 The copper protrusion on the TSV caused respectively by thermal expansion and diffusion of copper lattices and atoms may destroy stacked IC chips. [20][21][22] Copper must be replaced by tungsten 23 or nickel 24,25 to overcome the issue of CTE mismatch.Although the CTE of tungsten is very low, 14,26 it cannot be electrochemically plated in an aqueous electrolyte. Fortunately, tungsten can be induced to co-deposit with nickel. [27][28][29][30][31][32] In this work, a Ni-W alloy plating formula that can achieve Ni-W bottom-up filling of microvia was developed. This plating formula can fill the microvia of PCBs and can also fill TSVs. The Ni-W filled TSVs exhibit good thermal stability after being annealed at 500• C for 4 h. ExperimentalThe dimensions of the PCB fragments cut for the Ni-W filling plating were 4.2 × 6.0 cm 2 . The microvias were formed by CO 2 laser ablation. The diameter and depth of the microvias were 80 μm and 40 μm, respectively. The sidewalls of the microvias were metallized by electroless copper plating in advance to deposit a 2-3 μm thick layer of copper before the filling plating.TSVs were formed by a deep reactive ion etching (DRIE) process (i.e., the Bosch process). The thickness of the isolation layer (i.e., SiO 2 ) in the TSVs formed by thermal oxidation was approximately 1-3 × 10 3 Å. The barrier layer was a TiN film with a thickness of 500 Å, which was conformably deposited by atomic layer deposition (ALD) for 600 cycles. The seed layer was depo...

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Stacking Fault and Plastic Deformation Mechanism in Nano‐twinned Cu Pillar under Ultrahigh Stress

Fu,

Lee,

Chang

et al. 2024

Adv Eng Mater

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Nano‐twinned Cu pillar was fabricated on an as‐electroplated nano‐twinned Cu film, which preferentially grew in the {111} plane family. With a nano‐indentation device (Picoindenter), a vertical ultrahigh pressure of 5100 MPa was applied to the nano‐twinned Cu pillar. The twin lamellar grain was greatly deformed under that ultrahigh external stress. Consequently, the top surface plane was pressed into the lattice beneath to continuously form edge dislocations. Those dislocations were driven along the possible slip systems toward the outer surface of the first matrix lamella, corresponding to the plastic deformation. A dislocation‐mediated mechanism was proposed to explain the plastic deformation of the nano‐twinned Cu pillar. Three types of slip systems were identified for the created dislocations, each resulting in either the displacement on the first matrix lamellar grain or cross‐slip on the twin boundary. At the ultrahigh external pressure, as the dislocations slid through the twin boundary, they would dissociate to Shockley partial dislocations and alter the stacking sequence in the twin boundary, creating stacking faults. The resultant stacking faults in the twin boundary were observed in the TEM lattice images.This article is protected by copyright. All rights reserved.

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3D-interconnect: Visualization of extrusion and voids induced in copper-filled through-silicon vias (TSVs) at various temperatures using X-ray microscopy

Cited by 38 publications

References 3 publications

Lower Protrusion of a Copper-Nickel Alloy in a Through-Silicon via and Its Numerical Simulation

Lower Protrusion of a Copper-Nickel Alloy in a Through-Silicon via and Its Numerical Simulation

Microvia Filling with Nickel-Tungsten Alloy to Decrease the Coefficient of Thermal Expansion of Electronic Circuit Interconnections

Stacking Fault and Plastic Deformation Mechanism in Nano‐twinned Cu Pillar under Ultrahigh Stress

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