3D Integration-Present and Future

Jiang, T.; Luo, Shijian

doi:10.1109/eptc.2008.4763463

Cited by 30 publications

(10 citation statements)

References 8 publications

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“…Many publications over the last several years have indicated that companies are either already manufacturing 3D chips or have plans to do so in the near future [65][66][67][68][69][70][71][72][73][74][75][76][77][78]. Ultimately, the success of any manufacturable 3D integration solution rides on several factors: 1) the choice of TSV technology, which in turn is determined by its compatibility with the rest of the fabrication process, including the bonding stage and method, and the requirements that are placed upon it from a systems perspective; 2) the robustness and thermo-mechanical reliability of the fully integrated structure; and 3) cost/yield considerations.…”

Section: Discussionmentioning

confidence: 99%

3D integration review

Farooq¹,

Iyer²

2011

Sci. China Inf. Sci.

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3-D integration delivers value by increasing the volumetric transistor density with the potential benefit of shorter electrical path lengths through use of the shorter third dimension. Several researchers have studied various aspect of 3Di such as bonding level, through silicon via processes and integration, thermomechanical reliability of the vias, and the impact of the vias on devices. In this paper, we review some of the literature with a view to understanding the key options and challenges in 3Di. We also discuss some important applications of this technology, and the constraints that have to be overcome to make it work.

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Section: Discussionmentioning

confidence: 99%

3D integration review

Farooq¹,

Iyer²

2011

Sci. China Inf. Sci.

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“…PECVD is a preferred method due to its advantages of lower deposition temperature (350℃), wellestablished good adhesion and close CTE to silicon, and so on. [1].…”

Section: Introductionmentioning

confidence: 95%

“…It is believed that through silicon via (TSV) interconnection is the ultimate way for 3D integration due to its shortest interconnection distance and fastest speed. [1] There are several key steps involved in TSV processes which could successfully address the limitations of today's packaging technologies, including via forming, sidewall insulating, via filling, wafer thinning and wafer or die stacking. [2] Sidewall insulating is one of the challenging bottlenecks.…”

Section: Introductionmentioning

confidence: 99%

A new method to fabricate sidewall insulation of TSV using a parylene protection layer

Zhu

et al. 2009

2009 International Conference on Electronic Packaging Technology &Amp; High Density Packaging

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This paper focused on the process of forming sidewall insulation of through silicon via (TSV) which was a challenging bottleneck in 3D integration technologies. In traditional way, etching silicon oxide on via bottom would reduce the thickness of sidewall insulation layer inevitably, which might lead to the failure of TSV sidewall insulation and electrical interconnection characteristic.In this paper, the parylene-C (called parylene herein) film was used to cover the silicon oxide of via in the anisotropic etching process, which prevented the silicon oxide at the sidewall from being etched. Using this method, a well sidewall insulation layer was fabricated successfully. The sidewall thickness of oxide layer gained 0.93µm, 0.49µm, and 0.40µm at the top part, middle part of the via and the via-base respectively after etching process.

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“…Optimal 3-D design can be achieved by co-optimizing the architecture and technology at each stage of design. Wirebonding and TSV are the two common techniques to stack multiple dies forming a 3-D IC [9]. Although, wire-bonding is a cheap straightforward approach, it is only suitable for low-power and low-frequency ICs that need less inter-die connections.…”

Section: Introductionmentioning

confidence: 99%

Early estimation of TSV area for power delivery in 3-D integrated circuits

Khan

Reda

Hassoun

2010

2010 IEEE International 3D Systems Integration Conference (3DIC)

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To harness the full potential of 3-D integrated circuits, analysis tools for early design space exploration are needed. Such tools, targeting multiple design facets and cost trade-off analysis, would allow designers to arrive at major decisions regarding architecture and implementations fabrics. We focus in this paper on the efficient estimation of on-chip power delivery requirements consistent with supply noise limits. We propose a number of algorithms to find the minimum number of through-silicon vias (TSVs) that deliver power with acceptable IR drops. Minimizing the number of TSVs reduces the total silicon die area which is the main recurring cost during fabrication. To compute the TSV requirements realistically, we utilize power traces derived from benchmark-based functional behavior of processors. To speed-up our simulations, we develop a trace selection technique that utilizes the relevant portion of power traces representing the worst load for IR drops. The trace selection scheme reduces the number of simulations by 51×. Using these traces we find the best spatial allocation of TSVs for a 3-D implementation of a processor. The iterative algorithm can be run in approximately one hour on a 40-processor cluster.

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3D Integration-Present and Future

Cited by 30 publications

References 8 publications

3D integration review

3D integration review

A new method to fabricate sidewall insulation of TSV using a parylene protection layer

Early estimation of TSV area for power delivery in 3-D integrated circuits

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