3D integration approaches for MEMS and CMOS sensors based on a Cu through-silicon-via technology and wafer level bonding

Abstract

Technologies for the 3D integration are described within this paper with respect to devices that have to retain a specific minimum wafer thickness for handling purposes (CMOS) and integrity of mechanical elements (MEMS). This implies Through-Silicon Vias (TSVs) with large dimensions and high aspect ratios (HAR). Moreover, as a main objective, the aspired TSV technology had to be universal and scalable with the designated utilization in a MEMS/CMOS foundry. Two TSV approaches are investigated and discussed, in which the TSVs were fabricated either before or after wafer thinning. One distinctive feature is an incomplete TSV Cu-filling, which avoids long processing and complex process control, while minimizing the thermomechanical stress between Cu and Si and related adverse effects in the device. However, the incomplete filling also includes various challenges regarding process integration. A method based on pattern plating is described, in which TSVs are metalized at the same time as the redistribution layer and which eliminates the need for additional planarization and patterning steps. For MEMS, the realization of a protective hermetically sealed capping is crucial, which is addressed in this paper by glass frit wafer level bonding and is discussed for hermetic sealing of MEMS inertial sensors. The TSV based 3D integration technologies are demonstrated on CMOS like test vehicle and on a MEMS device fabricated in Air Gap Insulated Microstructure (AIM) technology

3D wafer level packaging technology based on the co-planar Au–Si bonding structure

“…With emerging on three-dimensional (3D) integration, the developments of vertical interconnections have been paid more attention than conventional way of horizontal interconnections, in which the through silicon via (TSV) technology is affecting profoundly on the semiconductor industries (More Than Moore's Law). Nowadays, the TSV technology has been applied to 3D stacks of IC and MEMS [10], e.g. DRAM, image sensors, pressure sensors, etc.…”

A Novel Seedless TSV Process Based on Room Temperature Curing Silver Nanowires ECAs for MEMS Packaging

“…As MEMS packaging evolves into miniaturization, TSV (through-silicon-vias) becomes a critical interconnection technology for MEMS packaging [1,2,3,4,5,6,7,8,9]. The current via-filling technique based on copper electroplating normally involves multi-step processes, including physical vapor deposition (PVD) or chemical vapor deposition (CVD) of barriers and copper seed layers, electroplating of copper plugs and the chemical mechanical polishing (CMP) process to remove the overburden layer and flatten the surface.…”

Approaches for wafer level packaging and heterogeneous system integration for CMOS and MEMS sensors

“…In addition to MEMS / CMOS processing, advanced technologies are required for wafer level packaging and heterogeneous system integration for achieving the needed sensor performance as well as packaging requirements. Different technologies have been developed in microelectronic and also MEMS industry and are described in literature 1,2 . Hereby, waferbonding technologies are most established processes for protection fragile micromechanical components and also for achieving the sensor functionality.…”