3D Integration and Characterization of High Q Passives on Multilayer Liquid Crystalline Polymer (M-LCP) Based Substrate

Yun, Wansuk; Bavisi, A.; Swaminathan, Madhavan; Engin, Ege

doi:10.1109/apmc.2005.1606257

Cited by 2 publications

(1 citation statement)

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“…Many proposed technologies focus mainly on passive device loss enhancement. This is the case for approaches that use high resistivity silicon HRS [1], SOI [2] or organic laminates [3] [4]. These technologies provide high-Q passive devices but fail to meet low-cost requirements and often need extra packaging steps for use.…”

Section: Introductionmentioning

confidence: 99%

3-D Multilayer Copper Interconnects for High-Performance Monolithic Devices and Passives

Ghannam

Bourrier

Ourak³

et al. 2013

IEEE Trans. Compon., Packag. Manufact. Technol.

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International audienceThis paper presents a new and efficient low-cost multi-layer 3D copper interconnect process for monolithic devices and passives. It relies on the BPN and SU-8 photoresists, associated with an optimized electroplating process to form multi-level 3D interconnects in a single metallization step. The SU-8 is used as a permanent thick dielectric layer which is patterned underneath specific locations to create the desired 3D interconnect shape. A 3D seed layer is deposited above the SU-8 and the substrate to insure 3D electroplating current flow. The BPN is used as a thick mold for copper electroplating with an aspect ratio as high as 16:1. An optimized 3D copper electroplating process is later used to grow 3D interconnects, insuring transition between all metallic layers. Finally, high-Q (55 @ 5 GHz) power inductors have been designed and integrated above a 50 W RF power LDMOS device, using this process

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