3D image segmentation implementation on FPGA using the EM/MPM algorithm

Sun, Yuxin; Christopher, Lauren

doi:10.1109/icassp.2010.5495113

Cited by 4 publications

(1 citation statement)

References 10 publications

(9 reference statements)

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“…The reconfigurable platform such as FPGA is a good alternative to CPU and GPU for EM-GMM training due to its hardware-based computing characteristic. Some work of optimizing EM-GMM on FPGA [18] [19] improves the performance a lot only certain circumstances, such as small dimension parameter, few samples. As the EM-GMM algorithm is not naturally fit into FPGA and the limited space of an FPGA chip can only fit designs with a small dimension (D) and component (K) parameter, there is much potential to further improve the performance if the EM-GMM algorithm can be transformed into a pipeline-friendly one.…”

Section: Existing Acceleration System For the Em-gmmmentioning

confidence: 99%

A Fully-Pipelined Hardware Design for Gaussian Mixture Models

Guo

et al. 2017

IEEE Trans. Comput.

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Abstract-Gaussian Mixture Models (GMMs) are widely used in many applications such as data mining, signal processing and computer vision, for probability density modeling and soft clustering. However, the parameters of a GMM need to be estimated from data by, for example, the Expectation-Maximization algorithm for Gaussian Mixture Models (EM-GMM), which is computationally demanding. This paper presents a novel design for the EM-GMM algorithm targeting reconfigurable platforms, with five main contributions. First, a pipeline-friendly EM-GMM with diagonal covariance matrices that can easily be mapped to hardware architectures. Second, a function evaluation unit for Gaussian probability density based on fixed-point arithmetic. Third, our approach is extended to support a wide range of dimensions or/and components by fitting multiple pieces of smaller dimensions onto an FPGA chip. Fourth, we derive a cost and performance model that estimates logic resources. Fifth, our dataflow design targeting the Maxeler MPC-X2000 with a Stratix-5SGSD8 FPGA can run over 200 times faster than a 6-core Xeon E5645 processor, and over 39 times faster than a Pascal TITAN-X GPU. Our design provides a practical solution to applications for training and explores better parameters for GMMs with hundreds of millions of high dimensional input instances, for low-latency and high-performance applications.

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Section: Existing Acceleration System For the Em-gmmmentioning

confidence: 99%